Storage System
bus
There are two kinds of interconnection between the members, the dispersion is connected, interconnected by a separate connection between the various components. Bus: each member is connected to a common set of information transfer lines.
characteristic
A.Physical characteristics(Geometric dimensions and shape of the connection type, number, connector)
B.Electrical Characteristics(A serial interface is lower than a predetermined low -3 V, represents a logical "1", a high level is higher than + 3V, said logic "0")
C.Features(Different control line functions, such as address lines used to transmit the address information, a data line for transmitting data information)
D.Time characteristics(The timing relationship between the signal generated by each line)
classification
A.The internal bus: Chip bus connecting the respective element.
B.System bus: Functional parts connected to the computer system. (Composition: a group of data lines, a set of control lines, a set of address lines）
C.Communication bus: Communications between the host and the I / O device or a computer system.
Bus data transmission mode
Serial transmission(Divided into synchronous mode and asynchronous mode) andParallel transmission。
Basic elements to consider when designing bus
(1) Type of signal lines: dedicated signal lines / signal lines multiplexed
(2) arbitration: centralized decision / verdict distributed
(3) timing modes: synchronization protocol info / asynchronous protocol info / semi-synchronous agreement / transaction agreement separation
(4) transaction types: bus supports various types of data transfer operations and other types of buses
(5) bus bandwidth: effective data per unit time on the bus
Bus ruling
Decide which bus master will receive the right to use the bus at the next process.
Each member is connected to the bus, the bus is divided according to their ability to control the presence or absenceMaster devicewithFrom equipmentTwo kinds.
Award program should be balanced. "Level of"with"Fairness”。
Centralized adjudication
Distributed adjudication
(1) Distributed bootstrap decision
(2) Distributed Conflict detection decision
(3) Parallel Distributed competitive award
Bus Architecture
(1) a single bus structure
(2) dual bus architecture
(3) three bus structure
Input / output device
classification
（1）input device: Keyboard, mouse, light pen, a touch screen, a track ball, a joystick, a digitizer, a scanner, a language input, handwriting character recognition, tape input unit, card machines, optical character reader
(2)Output Device: Monitor, printer, plotter, voice input device, a card puncher, paper tape puncher
(3)Input / output device: Disk, tape, read / write optical disk, CRT terminal, communication device
The type of printer
For impact, non-impact
Input / Output Organization
Basics
Function AI / O interface: data buffering, status or error detection, control and timing, data format conversion, and a host device in communication with the
BI / O interface is divided by the data transfer schemeParallel InterfacewithSerial Interface。
C.I / O portsIn fact, I / O interface of the various registers, such as a data buffer register, the control status register. An I / O port may be a port input port, an output port, or a bidirectional input can also be output.
DI / O port addressing two ways:Independent addressing mode (a dedicated input / output instructions), unified addressing mode。
Program interrupt
Interrupt classification
a.Internal interrupt: Interrupted by unusual events caused by the internal processor.
b.External interrupt: Peripherals to complete the task, or there are special circumstances caused.
Interrupt the basic functions of the system
a. timely recording the various interrupt request signal
b. automatically interrupt request
c. Automatic arbiter
d. breakpoints and protection field
e.Interrupt Mask:中断屏蔽机制，使得每个中断可以设置它允许被哪些中断打断，不允许被哪些中断打断，通过在中断系统中设置中断屏蔽字来实现。
中断过程
中断过程包括两个阶段：中断响应阶段和中断处理阶段。
中断响应阶段由硬件实现。
中断处理阶段则由CPU执行中断服务程序完成，由软件实现。
例题
假定某中断系统有四个中断源，其响应优先级为1>2>3>4。假定CPU在执行用户程序时，同时发生了1、3和4级中断请求，而在执行3级中断服务程序的过程中又发生了2级中断请求。
(1)写出处理优先级为1>2>3>4时各中断的屏蔽字及CPU完成中断服务程序的过程。
(2)写出处理优先级为1>4>3>2时各中断的屏蔽字及CPU完成中断服务程序的过程。
解：
(1)
（2）
DMA（直接存储器存取方式）
A.DMA方式用专门的DMA接口硬件来控制外设与主存间的直接数据交换。
B.三种DMA方式：CPU停止法、周期挪用法、交替分时访问法
C.DMA的总线优先权比CPU高.
D.DMA interface function
(1) sent to the receiving peripheral "DMA request" signal, and to send "bus request" signal to the CPU.
After (2) CPU issued a "Bus Response" signal, to take over control of the bus.
(3) gives the address of the main memory address line, and automatically modifying the memory address.
(4) identifying the transport direction to give the proper read and write control information in the control line
(5) to determine the number of bytes of data transmitted.
(6) a DMA end signal. Causing a DMA interrupt, data validation and some post-processing.
