FPGA code:
module down(
i_clk,//输入时钟
i_rst,//输入复位信号
i_M, //抽取值
i_data,//输入信号
o_data,//输出信号
r_clk
);
input i_clk;//输入时钟
input i_rst;//输入复位信号
input [7:0] i_M; //抽取值
input signed[31:0] i_data;//输入信号
output signed[31:0]o_data;//输出信号
output r_clk;//输出信号
reg [7:0] r_cnt =8'd0;
reg signed[31:0]o_data=32'd0;
reg r_clk =1'b0;
always @(posedge i_clk)
begin
if(!i_rst)//系统复位
begin
r_cnt<=8'd0;
r_clk<=1'b0;
end
else begin
if(r_cnt==i_M/2-1)//分频
begin
r_clk<=~r_clk;
r_cnt<=8'd0;
end
else begin
r_cnt<=r_cnt+1'b1;
r_clk<=r_clk;
end
end
end
always @(posedge r_clk)
begin
if(!i_rst)//系统复位
begin
o_data<=32'd0;
end
else begin
o_data<=i_data;//抽取
end
end
endmodule MATLAB code:
clc;
clear;
close all;
%CIC又称为梳状滤波器，所以这里首先给出其梳状波形。。。。
%积分滤波器的响应
b1=1;
a1=[1 -1];
D=9;
b2=[1 zeros(1,D-1) -1];
a2=1;
b3=b2;
a3=a1;
b4=conv(b3,b3);
a4=conv(a3,a3);
b5=conv(b4,b3);
a5=conv(a4,a3);
b6=conv(b4,b4);
a6=conv(a4,a4);
b7=conv(b6,b3);
a7=conv(a6,a3);
figure(1);
freqz(b7/D^5,a7,'whole');
%CIC抽取滤波器
% 抽取因子
r = 2;
hm = mfilt.cicdecim(r);
%原始的采样率 44.1kHz.
fs = 44.1e3;
%10240个采样点
n = 0:10239;
%原始信号
x = sin(2*pi*1e3/fs*n);
%得到抽取后的5120个采样点
y_fi = filter(hm,x);
x = double(x);
y = double(y_fi);
y = y/max(abs(y));
figure(2);
stem(n(1:44)/fs,x(2:45)); hold on;
stem(n(1:22)/(fs/r),y(3:24),'r','filled');
xlabel('时间(sec)');ylabel('信号值');
title('CIC抽取滤波器');
%CIC内插滤波器
%插值因子
R = 2;
hm = mfilt.cicinterp(R);
% 原始采样频率:22.05 kHz.
fs = 22.05e3;
% 5120个采样点
n = 0:5119;
%原始信号
x = sin(2*pi*1e3/fs*n);
y_fi = filter(hm,x);
x = double(x);
y = double(y_fi);
y = y/max(abs(y));
figure(3);
stem(n(1:22)/fs,x(1:22),'filled'); hold on;
stem(n(1:44)/(fs*R),y(4:47),'r');
xlabel('时间(sec)');ylabel('信号值');
title('CIC内插滤波器');Simulation and Description
1.1 MATLAB design description
The frequency characteristics of this CIC filter, if the picture above, the picture above is similar to the comb. So it is called a comb filter.
This is the CIC decimation filter. As you can see in the figure, one point is extracted every 2 points to achieve the extraction effect.
This is the CIC interpolation filter. As you can see in the figure, a point is inserted every 2 points to achieve the extraction effect.
1.2 FPGA Design Description
Generally, in practical applications, we mostly use more decimation filters. The general decimation filters are as follows:
Here, we concretize some of these parameters and design a CIC filter with specific parameters.
We make this system module, and then in practical application, we only need to change the parameters.
The system is divided into the following three modules.
The design of module one:
delay_one(
i_clk,//input clock
i_rst,//input reset signal
i_data,//input signal
o_data//output signal
);
The design of module two:
down(
i_clk,//input clock
i_rst,//input reset signal
i_M, // extract value
i_data,//input signal
o_data//output signal
);
The design of module three:
delay_M(
i_clk,// input clock
i_rst,// input reset signal
i_data,// input signal
o_data// output signal
);
Then it's at the top level, and we just need to call these modules.
The output of the CIC integrator is as follows:
The system filter output results are as follows:
You can see the effect after filtering.
When changing the number of CIC stages, CIC filters with different effects can be obtained
The fastest way to check the CIC filter is to input a step signal. Here the step signal we input is 00FFFFFF, and finally the effect of the CIC filter is like dataout. By looking at the relevant literature, the step signal passes through the CIC filter. The effect is:
The effect is basically the same as that obtained by our FPGA design.
The above is the filtering effect after inputting a random signal. Obviously, its waveform characteristics have been improved.
A01-23