VIVADO FIR filter design and simulation (1)
Introduction
FIR filter, that is, finite impulse response filter, as the name suggests, refers to the filter whose unit impulse response length is finite. According to the structural form of FIR filter, it is divided into direct type, cascade type, frequency sampling type and fast convolution type. Among them, the direct type can adopt serial structure, parallel structure and distributed structure. This example implements an FIR filter with a linear phase semi-serial structure.
This case is designed with the Block Design method.
signal source
In this case, the DDS IP core is used to generate two simple sine signals. For the convenience of later observation, a 4M and a 5M sine signal are respectively generated here.
Double-click to open the DDS IP core to enter the settings, and set the relevant parameters.
The relevant settings in this case are as follows:
After setting the relevant parameters, you can view the frequency information in Output Frequencies.
Similarly, view the set parameter information in the Summary option
mixing
Call a multiplier, mix the two sinusoidal signals, and observe the signal after mixing.
connect
After the IP module selection is completed, you can connect it. First, select the aclk pin of the DDS IP,
right-click the ackl pin, and click make external
to generate an aclk input pin, and then connect the aclk pin of another DDS IP core. Connect to the aclk input pin.
Then connect the M_ASIS_DATA output pins of the two DDS to A and B of the mult_gen IP core respectively. After that, right-click the P pin and select make external to automatically generate the output pin.
Right-click on the blank space and select valid design. The following window appears, indicating that there is no error in the connection.
After the connection is completed, ctrl+s saves the project, and then in the source window, there is an option similar to the pyramid shape.
This is the BD file of the project. Right-click, select create a HDL wapper, and generate a top-level file.
simulation
After the project is established, we write a TB file to simulate it. The test code is as follows:
module tb_top(
);
reg aclk_0 ;
wire [31:0]S_0;
initial
aclk_0 = 1;
always #5 aclk_0 = ~aclk_0 ;
DSP_TEST_wrapper DSP_TEST_wrapper_i
(.aclk_0(aclk_0),
.S_0(S_0));
endmoduleAdd the test file to the project, click run simulation on the left to simulate with modelsim (you need to associate VIVADO with modelsim, and set it in the SIMULATION option)
The simulation result is shown in the figure below (I also connected the two sine signals to the pins Come out, it is convenient for simulation observation, you can also add the DDS IP signal in modelsim to observe, the effect is the same)
