[FPGA] Verilog realize traffic lights

Sophomore curriculum design digital circuits, there is a daily job using Xilinx FPGA to achieve simple traffic lights, but unfortunately time was very limited and did not finalized. Just this semester elective course SOPC design, also using Xilinx FPGA, it intends to re-complete the relevant content of traffic lights.

This project uses the Digilent produced BASYS3 development board based on Xilinx FPGA, the board can now buy a home in Ma, but the price of your side, students can apply for a lower price to buy in digilent official website.

Following general framework, only a concept, is far from perfect, follow-up will be modified. For example, now I am currently not completely off the timer function module out from the State, but with 1s Timer instance of a timer inside, and with the count count.

 

Here is the code portion of the State, there are still many modifications need improvement, such subsequent count counter is also State will pick out. Notes due in part to the editor that comes with too Vivado knock chen (no way to font fallback), and I do not like Microsoft elegant black and Times New Roman, so I had to use my site to write a little English annotated.

module BASYS_BIGPROJECT_State(
input clk,
output reg[1:0]state,
output reg[3:0]count
    );
wire clk_1;
Freq_divider #(27)clk_1s(clk,0,,clk_1);
always@(posedge clk_1)
begin
    count <= count + 1;
end

//green led for 4s, yellow led for 2s
always@(posedge clk)
begin
    case(state)
    2'b00:begin //main red, branch green
        if(count<4) begin
            state <= 2'b00;
        end
        else begin
            state <= 2'b01;
            count = 3'b000;
        end
    end
    2'b01:begin //main red, branch yellow
        if(count<2) begin
            state <= 2'b01;
        end
        else begin
            state <= 2'b11;
            count = 3'b000;
        end
    end
    2'b11:begin //main green, branch red
        if(count<4) begin
            state <= 2'b11;
        end
        else begin 
            state <= 2'b10;
            count = 3'b000;
        end
    end
    2'b10:begin //main yellow, branch red
        if(count<2) initial 
            state <= 2 ' b10; 
        end 
        else  begin 
            state <= 2 ' b00; 
            count = 3 ' B000; 
        end 
    end 
    ENDCASE 
end 
endmodule