Digital Signal Processing for FPGAs: Simple FIR Filter Implementation in Verilog

This project shows how to implement a simple FIR filter with pregenerated coefficients using Verilog.

introduction

The humble FIR filter is one of the most basic building blocks in FPGA digital signal processing, so it's important to understand how to combine basic building blocks with a given number of taps and their corresponding coefficient values. Therefore, in this practical introduction to the basics of DSP on an FPGA, you will start with a simple 15-tap low-pass filter FIR, generate initial coefficient values ​​for it in Matlab, and then convert these values ​​for writing a Verilog module.

A finite impulse response, or FIR filter, is defined as a filter whose impulse response is stable at zero for a specified period of time. The time it takes for the impulse response to settle to zero is directly related to the filter order (number of taps), which is the order of the FIR's underlying transfer function polynomial. The transfer function of the FIR does not include feedback, so if the input is a pulse with a value of 1, and then a series of zeros, the output will be only the coefficient values ​​of the filter.

The role of the filter is basically used for signal conditioning, mainly focusing on selecting which frequencies to filter out or allow to pass. One of the simplest examples is a low-pass filter, which allows frequencies below a certain threshold (cutoff frequency) to pass while greatly attenuating frequencies above that threshold, as shown in the figure below.

The main focus of this project is the implementation of FIR in HDL (Verilog specifically), which can be broken down into three main logical components: a circular buffer to clock each sample to the appropriate