Verilog HDL Quick Start 4: always process, condition, judgment, loop statement, function, task module

table of Contents

One or two always processes

Two, if-else statement

Three, case statement

Three, loop loop statement

Four, verilog other sub-modules

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One or two always processes

note:

1. The always block is triggered only when the variables in the sensitive list change (* represents all variables)

2. In the sequence process in the example: sensitive to rising and falling edges

Two, if-else statement

It is exactly the same as the c language!

Three, case statement

Statement derived from case statement

Three, loop loop statement

Four, verilog other sub-modules