1, in STM32F4, five most important source clock for HSI, HSE, LSI, LSE, PLL. Wherein the PLL is actually divided into two clock sources, the main PLL, and a dedicated PLL.
2, ①, LSI low speed internal clock, the RC oscillator frequency of about 32kHz. Independent watchdog for automatic wakeup unit and used.
②, LSE is a low-speed external clock, then the frequency of 32.768kHz quartz crystal. This is mainly the RTC clock source.
③, HSE high speed external clock, may be connected to a quartz / ceramic resonator, or access an external clock source, the frequency range of 4MHz ~ 26MHz. Our "Explorer" my board is 8M crystal. HSE may be directly used as the system clock or PLL input.
④, HSI high-speed internal clock, the RC oscillator frequency of 16MHz. PLL clock can be input directly or as a system.
⑤, PLL phase-locked loop frequency output. STM32F4 two PLL:
1) Main PLL (PLL) clocked by HSE or HSI, and having two different output clocks:
PLLP first output clock for generating a system speed (up to 168MHz);
A second output for generating a USB OTG FS PLLQ clock (48MHz), the random number generator clock and the clock SDIO.
2) Dedicated PLL (PLLI2S) for generating an accurate clock, so that high quality audio interface performance I2S.
3, here remember, AHB maximum clock is 168MHz, APB2 maximum clock frequency of the high-speed 84MHz, and low-speed clock APB1 maximum frequency of 42MHz.
4, the clock source on I2S:
I2S PLLI2S clock source from external clock or mapped to I2S_CKIN pin. I2S consideration for sound quality, high precision clock. Explorers STM32F4 development board using an internal PLLI2SCLK.
5, on the internal clock STM32F4 Ethernet MAC:
For the MII interface, it must provide the 25Mhz clock, the external clock to the PHY chip by the PHY chip may be an external crystal oscillator, or used to provide STM32F4 MCO output. Then, PHY chips provide ETH_MII_TX_CLK give STM32F4 and ETH_MII_RX_CLK clock.
For RMII interface, it must provide an external clock driver and a PHY ETH_RMII_REF_CLK STM32F4 of 50Mhz, 50Mhz clock that may be derived from a PHY, or MCO STM32F4 the active crystal. Our development board using the RMII interface, use PHY chip provides 50Mhz clock driver ETH_RMII_REF_CLK STM32F4 of.
In the above clock output, with many of enabling control, e.g. AHB bus clock, the core clock, APB1 variety of peripherals, the peripherals APB2 and the like. A module when required, must first remember that the clock can cope.