stm32f10x clock system (1)

Clock Block Diagram Description

The block diagram of the stm32f10x clock system is as follows:

The blue quadrilateral is the clock source, the gray quadrilateral is the selector, and the other color is the (pre)scaler; for example, 32MHz divided by two is 16MHz.

5 clock sources, one system clock (SYSCLK)

HSI: High-speed internal clock (about 8MHz); generated by the RC oscillator, the clock generated by the RC oscillator is unstable

HSE: High-speed external clock (4~16M, 8M for punctual atoms), generated by crystal oscillator

PLL: phase-locked loop; used for frequency multiplication (2~16 times), output a PLLCLK clock

The above three clocks can be used as the source of the system clock.

CSS: Clock Monitoring System. What is it good for? Generally speaking, the HSE clock is selected as the system clock, but because the clock source of the HSE is external; some accidents may occur: for example, the crystal oscillator does not vibrate; at this time, the CSS will select the HSI as the system clock.

LSE: low-speed external clock, the frequency is generally: 32.768KHz, generated by an external crystal oscillator. Generally used for RTCCLK; RTCCLK is real-time clock,
LSI: low-speed internal clock, frequency is about 40KHz, generated by RC oscillator; the main function is used for independent watchdog clock

The above are the five clock source signals.

MCO is a pin, corresponding to PA8, it can output clock signal; including: SYSCLK, HSI, HSE, PLLCLK/128

USB clock: PLLCLK is obtained through the USB frequency divider (1 or 1.5 times); the USB clock is 48MHz, and the clock signal of PLLCLK is 72MHz or 48MHz. If it is 72MHz, then the USB frequency divider is set to 1.5 times the frequency division, if it is 48MHz, then the USB frequency divider is set to 1 times the frequency

The SYSCLK clock passes through the AHB prescaler (the division factor is 1, 2, 4, 8, 16, 32, 64, 128, 256) to give the HCLK clock; The clock is used for the low-speed devices attached to the APB1 bus, or the APB2 prescaler becomes a 72MHz clock signal for the high-speed devices attached to the APB2 bus.

summary

1. STM32 has 5 clock sources: HSI, HSE, LSI, LSE, PLL.
   
   • HSI is a high-speed internal clock, RC oscillator, with a frequency of 8MHz, and the accuracy is not high.
   • HSE is a high-speed external clock, which can be connected to a quartz/ceramic resonator, or an external clock source, with a frequency range of 4MHz~16MHz.
   • LSI is a low-speed internal clock, RC oscillator, with a frequency of 40kHz, providing a low-power clock. WDG
   • LSE is a low-speed external clock connected to a quartz crystal with a frequency of 32.768kHz. RTC,
   • PLL is a phase-locked loop frequency multiplication output, and its clock input source can be selected as HSI/2, HSE or HSE/2.
     The frequency multiplier can be selected from 2 to 16 times, but the maximum output frequency should not exceed 72MHz.
2. The system clock SYSCLK can be derived from three clock sources:
   
   • HSI oscillator clock
   • HSE oscillator clock
   • PLL clock

3. STM32 can select a clock signal to output to the MCO pin (PA8), which can be selected as the PLL
   output divided by 2, HSI, HSE, or system clock.

4. Before any peripheral can be used, its corresponding clock must be enabled first.

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Several commonly used registers:

• AHBENR register: DMA, SDIO and other clock enable
• APB1ENR register: Peripheral clock enable on APB1 bus
• APB2ENR register: peripheral clock enable on APB2 bus
• CR register: enable and ready flags of HSI, HSE, CSS, PLL, etc., because some clock sources may not be stable immediately after being enabled, it takes a while, and when stable, it will be set in the corresponding position of the register , you can know whether the clock source is stable by checking the value of the register
• CFGR register: The selection of the clock source and the setting of the frequency division factor can be seen in the figure above.

library function version

The above registers have corresponding library functions that can be called in the library function version.

• Clock enable configuration:
  RCC_LSEConfig() , RCC_HSEConfig() ,
  RCC_HSICmd() , RCC_LSICmd() , RCC_PLLCmd()  …
• Clock source related configuration:
  RCC_PLLConfig(), RCC_SYSCLKConfig(),
  RCC_RTCCLKConfig() …

• Frequency division factor selection configuration:
  RCC_HCLKConfig() , RCC_PCLK1Config() , RCC_PCLK2Config()…

• Peripheral clock enable:
  RCC_APB1PeriphClockCmd(): //Enable peripheral clock on APB1 line
  RCC_APB2PeriphClockCmd(); //Enable peripheral clock on APB2 line RCC_AHBPeriphClockCmd(); //Enable peripheral clock on
  AHB line

• Other peripheral clock configuration:
  RCC_ADCCLKConfig(); RCC_RTCCLKConfig();

• Status parameter acquisition parameters:
  RCC_GetClocksFreq();
  RCC_GetSYSCLKSource();
  RCC_GetFlagStatus()

• RCC interrupt related functions:
  RCC_ITConfig() , RCC_GetITStatus() , RCC_ClearITPendingBit()…

The functions of the previous system initialization are set in the official firmware library of ST, and the registers set directly, so you do not need to manually enable it yourself

References

• Punctual Atomic Video
• stm32 Chinese Reference Manual