STM32 learning experience seven: STM32 clock system block diagram and interpret the correlation function

Record it, to facilitate future ~ read
main content :
1) Reading clock system block diagram;
2) System Configuration Clock correlation function interpretation.
Official information: "STM32 Chinese Reference Manual V10" Chapter VI reset and clock control RCC
1. Why STM32 multiple clock sources have it?
Because the STM32 is very complex, peripherals and more, but not all the peripherals require such a high frequency system clock, for example, only need watchdog and RTC clock to tens of k. The same circuit, a clock faster the larger the power consumption, immunity to electromagnetic interference while also weaker, so for more complex multi-MCU clock source in general, a method to solve these problems.
2. Interpretation clock system diagram
Here Insert Picture Description 1) STM32 five clock sources: the HIS (High Speed Internal), the HSE (High Speed External), the LSI (Internal Low Speed), the LSE (External Low Speed), the PLL:
1.1 high speed inside the HSI clock, the RC oscillator frequency is approximately 8MHz, accuracy is not high, as the system clock;
1.2 the HSE is a high speed external clock, may be connected to a quartz / ceramic resonator, or receive an external clock source, the frequency range of 16MHz ~ 4MHz;
1.3 the LSI low-speed internal clock, the RC oscillator frequency of 40kHz, provides a low power clock. Independent watchdog clock source only LSI, LSI can simultaneously also serve as a source for the RTC clock;
1.4 the LSE is a low-speed external clock, then the frequency of 32.768kHz quartz crystal, mainly as a source for the RTC clock;
for 1.5 to lock the PLL ring frequency output, its clock input source selected to HSI / 2, HSE or HSE / 2. Alternatively multiplier 2 to 16 times, but it must not exceed the maximum output frequency is 72MHz.
2) MCO is a clock output STM32 IO (PA8 connected to the pin) to select a clock signal output (e.g. frequency-divided output of the PLL 2, HSI, HSE, or the system clock), the external clock can be used to other systems provide a clock source;
. 3) Alternatively the RTC clock source LSI, LSE, HSE and divided by 128;
. 4) of the USB clock source from PLL clock, the STM32 there is a full speed USB module function, which requires a serial interface engine a source of clock frequency of 48MHz. The clock source can be obtained from the output of PLL, optionally 1.5 or 1 divider dividing, i.e., when it is desired to use the USB module, PLL must be enabled, and the clock frequency of 48MHz or configured 72MHz;
. 5) for the system clock SYSCLK STM32 clock source of the majority of the work member. The system clock SYSCLK optionally PLL output, HSI or HSE. The maximum frequency of 72MHz;
. 6) of the clock source other peripherals are SYSCLK. AHB SYSCLK by the frequency divider to the respective module, comprising:
HCLK 6.1 AHB bus clock, the kernel, and memory used by DMA;
6.2 Cortex to the division by 8 system timer clock, i.e. SysTick;
6.3 Cortex directly to the free-running clock FCLK;
6.4 give APB1 divider. APB1 way for APB1 divider output peripherals (PCLK1, the maximum frequency of 36MHz), the other way to the timer (Timer) 2,3,4 doubler;
6.5 gave APB2 divider. APB2 frequency divider to output one for APB2 peripherals (PCLK2, the maximum frequency of 72MHz), the other way to the timer (Timer) 1 doubler.
Connections 7) APB1 above is the low-speed peripherals, including power interface, the backup interface, CAN, USB, I2C1, I2C2 , UART2, UART3 the like, is connected to the above high speed peripherals include APB2 UART1, SPI1, Timer1, ADC1, ADC2 , all common IO port (PA ~ PE), etc. the second function IO port;
. 8) the CSS clock monitoring system, once the HSE failure, automatically switches to the HIS = the SYSCLK;
. 9) before the use of any peripheral, must enable their respective clock;
10) five main clock:
10.1 the SYSCLK (system clock);
10.2 the AHB bus clock;
10.3 the APB1 bus clock (low speed): speed up to 36MHz;
10.4 APB2 and bus clock (high speed): speed up to 72MHz;
10.5 PLL clock.
3. Clock configuration register

typedef struct
{
  __IO uint32_t CR;                //HSI,HSE,CSS,PLL等的使能和就绪标志位 
  __IO uint32_t CFGR;             //PLL等的时钟源选择,分频系数设定
  __IO uint32_t CIR;               // 清除/使能 时钟就绪中断
  __IO uint32_t APB2RSTR;        //APB2线上外设复位寄存器
  __IO uint32_t APB1RSTR;        //APB1线上外设复位寄存器
  __IO uint32_t AHBENR;          //DMA,SDIO等时钟使能 
  __IO uint32_t APB2ENR;         //APB2线上外设时钟使能 
  __IO uint32_t APB1ENR;         //APB1线上外设时钟使能
  __IO uint32_t BDCR;            //备份域控制寄存器
  __IO uint32_t CSR;             //控制状态寄存器
} RCC_TypeDef;

4. RCC related firmware library header files and source files
4.1 clock enable configuration:
RCC_LSEConfig (), RCC_HSEConfig (), RCC_HSICmd (), RCC_LSICmd (), RCC_PLLCmd () ......
4.2 clock source configuration:
RCC_PLLConfig (), RCC_SYSCLKConfig ( ), RCC_RTCCLKConfig () ...
4.3 division factor selected configuration:
RCC_HCLKConfig ()
, RCC_PCLK1Config (), RCC_PCLK2Config () ...
4.4 peripheral clock enable:

RCC_APB1PeriphClockCmd();    //APB1线上外设时钟使能
RCC_APB2PeriphClockCmd();    //APB2线上外设时钟使能
RCC_AHBPeriphClockCmd();     //AHB线上外设时钟使能

4.5 Other peripheral clock configuration:
RCC_ADCCLKConfig (), RCC_RTCCLKConfig ();
4.6 state parameter acquisition parameters:
RCC_GetClocksFreq (), RCC_GetSYSCLKSource (), RCC_GetFlagStatus ();
4.7 Interrupt the RCC related functions:
RCC_ITConfig (), RCC_GetITStatus (), RCC_ClearITPendingBit () ...
knowledge points :
1) familiar with the system block diagram of the clock.

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