STM32 clock

Why configure the clock

• The registers of the microcontroller are composed of D flip-flops. To write something into the flip-flops, the premise is that there is a clock input.
  The 51 single-chip microcomputer does not need to configure the clock, because all functions can be used after a clock is turned on, but it has been consuming energy.
• The reason why stm32 is low power is that it sets all gates to disable by default. When you need to use which gate, you can open which gate, that is to say, what peripheral is used, just turn on the clock of the corresponding peripheral. That's ok, the other ones that are not used can still be disabled, so that the energy consumption will be reduced.

clock configuration

1. Turn on the high-speed clock HSE

// Set the clock control register RCC_CR bit 16 to 1 to enable

    RCC->CR|= 0x00010000;

• Bit 16: HSEON: External High Speed ​​Clock Enable When entering Standby and Stop modes, this bit is cleared by hardware to disable the 4-16MHz external oscillator. This bit cannot be cleared when the external 4-16MHz oscillator is used or selected to be the system clock.

2. Wait for the high-speed clock to be ready

// Read the clock control register RCC_CR bit 17 to 1 in place

while(!(RCC-> CR>>17)); 

• Bit 17: HSERDY: External High Speed ​​Clock Ready Flag is set by hardware to indicate that the external 4-16MHz oscillator is stable. This bit requires 6 external 4-25MHz oscillator cycles to clear after the HSEON bit is cleared.

3. Set the APB1, APB2, AHB frequency division coefficients

// set clock configuration register

   RCC_CFGR RCC_CFGR=0x00000400;

(AHB: bits 4-7, (low speed) APB1: bits 8-10, (high speed) APB2: bits 11-13)

• Bits 7:4: HPRE[3:0]: AHB Prescaler (AHB Prescaler) 0xxx: SYSCLK not divided
• Bits 10:8: PPRE1[2:0]: Low Speed ​​APB Prescaler (APB1) 100: HCLK Divide by 2
• Bits 13:11: PPRE2[2:0]: High-speed APB prescaler (APB2) 0xx: HCLK not divided

4. Set PLL multiplier // Configure clock configuration register RCC_CFGR bits 18-21

    RCC_CFGR|=7<<18;

• Bits 21:18: PLLMUL: PLL multiplier factor 0111: PLL multiplier output by 9

5. PLL input clock source selection

//Configure the clock configuration register RCC_CFGR bit 16

RCC_CFGR|=1<<16; 

• Bit 16: PLLSRC: PLL
  entry clock source 1: HSE clock as PLL input clock. Set to '1' or cleared to '0' by software to select the PLL
  input clock source. This bit can only be written when the PLL is turned off

6. Set the FLASH delay period

// 48

    FLASH->ACR|=0x32; 

7. PLL enable

// set clock control register RCC_CR bit 24

    RCC_CR|=0X01000000; 

• Bit 24: PLLON: PLL Enable 1: PLL Enable This bit is
  cleared . This bit cannot be cleared when the PLL clock is used or selected to be the system clock.

8. Wait for the PLL to be ready

// Set the clock control register RCC_CR bit 25 to 1 to lock

while(!(RCC_CR>>24)); 

• Bit 25: PLLRDY: PLL Clock Ready Flag 1: PLL Lock Set by hardware after PLL lock.

19. Set PLL as system clock

// configure the clock configuration register RCC_CFGR bits 0-1 :10

RCC_CFGR|=0X00000002; 

• Bits 1:0 SW[1:0]: System clock switch 10: PLL output as system
  clock Forced selection of HSI by hardware as system clock upon return from stop or standby mode or failure of HSE directly or indirectly as
  system clock Clock (if the clock security system has been activated)

10. Wait for the system clock to stabilize

// View clock configuration register RCC_CFGR bits 2-3:10

while((RCC->CFGR & (uint32_t)0x0c) != (uint32_t)0x08)

• Bits 3:2: SWS[1:0]: System clock switching status 10: PLL output as system clock; set to '1' or cleared to '0' by hardware to indicate which clock source is used as system clock