Establish "Drivers" under "Template_0" file folder to hold the driver code
In the "Drivers" folder under the new "M429_SysTick.h" and "M429_SysTick.c", adding "M429_SysTick.c" file to the "Drivers" packet
Open the "Options for Target 'Target 1'" => C / C ++, adding ".. \ Drivers" directory containing
SystickInit function definition:
. 1 int M429_SystickInit (uint32_t plln, PLLM uint32_t, uint32_t PLLP, uint32_t pllq) 2 { . 3 HAL_StatusTypeDef RET = HAL_OK; . 4 RCC_OscInitTypeDef RCC_OscInitStructure; . 5 RCC_ClkInitTypeDef RCC_ClkInitStructure; . 6 . 7 __HAL_RCC_PWR_CLK_ENABLE (); // enable clock PWR . 8 . 9 // following arranged to set the output voltage level of the regulator, so that the device is not running at maximum frequency 10 // performance and power consumption to achieve equilibrium, and this feature is only STM32F42xx STM32F43xx devices have, . 11 __HAL_PWR_VOLTAGESCALING_CONFIG (PWR_REGULATOR_VOLTAGE_SCALE1); // set the tone voltage output voltage level 1 12 is 13 is = RCC_OSCILLATORTYPE_HSE RCC_OscInitStructure.OscillatorType; // clock source to the HSE 14 RCC_OscInitStructure.HSEState = RCC_HSE_ON; // open the HSE 15 RCC_OscInitStructure.PLL.PLLState = RCC_PLL_ON; // open the PLL 16 RCC_OscInitStructure.PLL.PLLSource = RCC_PLLSOURCE_HSE; // the PLL clock source select the HSE . 17 RCC_OscInitStructure.PLL.PLLM = PLLM; // main audio and the PLL frequency division factor PLL (PLL before division), in the range:. 2 ~ 63 is 18 is RCC_OscInitStructure.PLL.PLLN = plln; // primary PLL . multiplication factor (PLL frequency) range: 64 ~ 432 . 19 RCC_OscInitStructure.PLL.PLLP = PLLP; //Main system clock PLL division ratio (after frequency division PLL), Range: 2,4,6,8 (four values only!). 20 is RCC_OscInitStructure.PLL.PLLQ = pllq; // the USB / main SDIO / random number generator like a PLL frequency coefficient (after division PLL frequency) range: 2 ~ 15. 21 is RET = HAL_RCC_OscConfig (& RCC_OscInitStructure); // initialize 22 is 23 is IF (RET = HAL_OK!) the while ( . 1 ); 24 25 RET = HAL_PWREx_EnableOverDrive (); // open Over-Driver function 26 is IF (RET = HAL_OK!) the while ( . 1 ); 27 28 // select the PLL as the system clock source and configured HCLK, PCLK1 and PCLK2 29 = RCC_ClkInitStructure.ClockType (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); 30 RCC_ClkInitStructure.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // set the system clock to increase the PLL 31 is RCC_ClkInitStructure.AHBCLKDivider = RCC_SYSCLK_DIV1; // the AHB frequency division factor. 1 32 RCC_ClkInitStructure.APB1CLKDivider = RCC_HCLK_DIV4; // the APB1 frequency division factor. 4 33 is RCC_ClkInitStructure.APB2CLKDivider = RCC_HCLK_DIV2; // APB2 and the frequency division factor of 2 34 is RET = HAL_RCC_ClockConfig (& RCC_ClkInitStructure, FLASH_LATENCY_5); // set the delay time period while FLASH 5WS, i.e. 6 CPU cycles. 35 36 IF(right! = HAL_OK) while ( 1 ); 37 38 return the right; 39 }
Use HAL library configuration STM32F429 General Procedure System clock:
1. Enable PWR clock
. 1 __HAL_RCC_PWR_CLK_ENABLE (); // enable clock PWR
To enable reason PWR clock, because the following step "Set regulator output level", and "Open Over-Driver function" is the power control configuration, it is necessary to open the PWR clock.
2. Set the level of the output voltage regulator
1 __HAL_PWR_VOLTAGESCALING_CONFIG (PWR_REGULATOR_VOLTAGE_SCALE1); // set the output voltage level regulator 1
Regulator output voltage level of the VOS , it is PWR-> CR bits 15:14 determined:
If the desired system clock 180M, you need to set a voltage level, and the open Over-Driver function.
3. Initialize the RCC oscillator
. 1 RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSE; // clock source to the HSE 2 RCC_OscInitStructure.HSEState = RCC_HSE_ON; // open the HSE . 3 RCC_OscInitStructure.PLL.PLLState = RCC_PLL_ON; // open the PLL . 4 RCC_OscInitStructure.PLL.PLLSource = RCC_PLLSOURCE_HSE; // the PLL clock source select the HSE . 5 RCC_OscInitStructure.PLL.PLLM = PLLM; // main audio and the PLL frequency division factor PLL (PLL before division), in the range:. 2 ~ 63 is . 6 RCC_OscInitStructure.PLL.PLLN = plln; // main . PLL frequency multiplication factor (PLL frequency) range: 64 ~ 432 . 7 RCC_OscInitStructure.PLL.PLLP = PLLP; //Main system clock PLL division ratio (after frequency division PLL), Range: 2,4,6,8 (four values only!). . 8 RCC_OscInitStructure.PLL.PLLQ = pllq; // the USB / main SDIO / random number generator like a PLL frequency coefficient (after division PLL frequency) range: 2 ~ 15. . 9 RET = HAL_RCC_OscConfig (& RCC_OscInitStructure); // initialize 10 . 11 IF (RET = HAL_OK!) the while ( 1 );
4. Select Open Over-Driver function.
. 1 RET = HAL_PWREx_EnableOverDrive (); // open Over-Driver function 2 IF (! = HAL_OK RET) the while ( . 1 );
5. Initialize the CPU, AHB and APB bus clock.
1 // Select PLL as the system clock source and configured HCLK, PCLK1 and PCLK2 2 RCC_ClkInitStructure.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); . 3 RCC_ClkInitStructure.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // set the clock source for the system clock PLL . 4 RCC_ClkInitStructure. = RCC_SYSCLK_DIV1 AHBCLKDivider; // the AHB frequency division factor. 1 . 5 RCC_ClkInitStructure.APB1CLKDivider = RCC_HCLK_DIV4; // the APB1 frequency division factor. 4 . 6 RCC_ClkInitStructure.APB2CLKDivider = RCC_HCLK_DIV2; // APB2 and frequency division factor 2 . 7 RET = HAL_RCC_ClockConfig (& RCC_ClkInitStructure, FLASH_LATENCY_5 ); //FLASH also set the delay period 5WS, which is 6 CPU cycles. . 8 . 9 IF (RET = HAL_OK!) The while ( . 1 );