Stm32's clock system and the use of SysTick tick timer to achieve delay

foreword

• The STM32 clock system consists of multiple clock sources and clock trees
• Clock sources include main clock source (HSE), internal high-speed clock source (HSI), internal low-speed clock source (LSI) and external low-speed clock source (LSE).
• The clock tree consists of multiple clock dividers and clock gates, which can divide the input clock source to obtain multiple clock signals, and open or close the clock gates as required to control the output of clock signals.

The following is what I queried from AI, I think it is still very informative

The main clock source of STM32 is HSE, which can be input through an external crystal oscillator or an external clock signal. The internal high-speed clock source HSI is 8MHz, and the switch can be controlled by the RCC_CR register. The internal low-speed clock source LSI is 40kHz, which is mainly used for the RTC module. The external low-speed clock source LSE is 32.768kHz, which is also used for the RTC module.

The clock tree mainly consists of the following parts:

1. System clock divider (SYSCLK): used to divide the frequency of the main clock source or internal high-speed clock source to obtain the system clock (SYSCLK).

2. AHB bus clock divider (HCLK): used to divide the system clock to obtain the AHB bus clock (HCLK).

3. APB1 bus clock divider (PCLK1): used to divide the AHB bus clock to obtain the APB1 bus clock (PCLK1).

4. APB2 bus clock divider (PCLK2): used to divide the AHB bus clock to obtain the APB2 bus clock (PCLK2).

5. Clock gate controller: used to control the clock switch of each peripheral, thus saving power consumption.

下面对Stm32的时钟系统做一个系统性的复习和总结

Stm32 clock system

时钟系统,理解时钟，看那个CubeMX时钟配置较为方便，虽然还是比较喜欢使用标准库哈哈

In Stm32, there are five clock sources, namely

HSI、HSE、LSI、LSE、PLL

• From the perspective of clock frequency, it can be divided into high-speed clock source and internal clock source

  HSI, HSE, PLL are high-speed clocks, LSI and LSE are low-speed clocks

• From the source point of view, it is divided into external clock source and internal clock source

  HSE and LSE are external clock sources, others are internal clock sources

HSI High Speed ​​Internal Clock

HSI is高速内部时钟，RC振荡器，频率为8MHZ

Generated by the internal 8MHZ RC oscillator

can be used directly as 系统时钟, or二分频作为PLL输入

Look at the picture below and it will be clear

HSE High Speed ​​External Clock

HSE is 高速外部时钟, his clock signal is generated by the following two clock sources

• HSE external crystal/ceramic resonator, to put it simply, it is a crystal oscillator
• HSE user external clock

The range of this frequency is 4MHZ-16MHZ

Generally connected to 8MHZ crystal oscillator

PLL phase-locked loop multiplier output

PLL is a phase-locked loop frequency multiplier output, and the input of PLL is optional

• Input after HSI two frequency division
• HSE input
• Input after HSE two frequency division

倍频可以选择2-16倍频，但是最大的输出频率不能超过72MHZ

The selection of the clock and the selected multiplication factor must be done before it can be activated

If you want to use the USB port, the PLL must be set to a 48 or 72MHZ clock to provide a 48MHZ USBCLK clock

LSE Low Speed ​​External Clock

LSE is a low-speed external clock, connected to an external crystal oscillator, the frequency is 32.768KHZ

It provides a low-power and accurate clock source for 实时时钟RTC, or其他定时功能

LSI low-speed internal clock

LSI is 低速内部时钟，RC震荡器，频率为40KHZ, the clock source of the independent watchdog can only be LSI, and LSI is a low-power clock source

It can keep running in shutdown and standby mode, for 独立看门狗and自动唤醒单元提供时钟

SYSCLK System clock selection

The clock source of the system clock SYSCLK can be the following

• HSI high speed internal clock 8MHZ
• HSE high speed external clock 8MHZ
• PLL phase-locked loop output 8MHZ-72MHZ (maximum can not exceed 72MHZ)

The clock source of all peripherals in the system comes from SYSCLK, and SYSCLK is sent to each module after frequency division by AHB clock

in

• AHB bus, core, memory and DMA use HCLK clock
• Divide by 8 to the system clock, which is systick, tick clock
• To Cortex free-running clock FCLK
• APB1 Peripheral Clocks and Timers 2-7
• APB2 Peripheral Clock and Timer 1 and Timer 8
• ADC, can divide frequency by 2, 4, 6, 8, ADCCLK maximum 14MHZ

RTC real time clock

RTC real-time clock, there are the following three sources

• HSE 128 frequency division
• LSE as the input of RTC clock
• LSI as the input of RTC clock

CSS Clock Security System

Generally speaking, the clock of the MCU basically comes from the external crystal oscillator 8MHZ, and after the frequency multiplication of the PLL phase-locked loop, it is passed to the system clock

But if the crystal oscillator circuit has an error and cannot produce an accurate clock, then CSS will work

He will automatically switch the system clock to HSIthe internal high-speed crystal oscillator with a frequency of 8MHZ

MCO internal clock output pin

MCU allows output clock signal to external MCO pin, this pin is PA8

The MCO clock output pin can output

• PLL phase-locked loop frequency division by 2
• HSI internal high speed clock
• HSE External High Speed ​​Clock
• SYSCLK system clock

STM32 clock block diagram

The role of STM32 startup files and the meaning of CL, VL, XL, LD, MD, HD

The function of the startup file, in Stm32f10x_hd.s, has been introduced in detail in the file comment, and has been translated as follows

• Set the initial stack top pointer SP
• Set the initial PC, let its initial value be Reset Handler
• Set vector table entries other than ISR address
• Configure the clock system and configure the external clock system at the same time
• The SRAM installed on the STM3210E-EVAL board is used as data memory (optional, determined by the user)
• Call the main() function in the C library
• After reset, the CortexM3 processor is in thread mode, the priority is Privileged, and the stack Stack is set to Main

in general

• Initialize the stack pointer and necessary routines
• Enter the main() function from the Systeminit() function (for stm32, define the system clock and first modify the macro in the system_stm3210x.c file)
• Establish interrupt service entry address (link interrupt vector and interrupt service function)

Meaning of CL, VL, XL, LD, MD, HD files

Stm32 is divided into different products according to different usage scenarios and the size of FLASH, and the abbreviations of different products are different

• CL : Interconnect products, Stm32F105/107 series
• VL: value-added products, Stm32F100 series
• XL : ultra-high precision products, Stm32F101/103 series
• LD : low-density products, FLASH less than 64k
• MD: medium density products, FLASH is equal to 64K or 128K
• HD: high-density products, FLASH greater than 128K

SysTick tick timer

SysTick is mainly used for delay, or the heartbeat clock of the real-time system, which can save MCU resources and not waste a timer

• SysTick is one 24位的到倒计数定时器, when the count reaches 0, it will automatically reload the timing initial value from the RELOAD register and start a new round of counting. As long as the enable bit in the SysTick control and status register is not cleared, it will never stop

• Works even in sleep state

Use SysTick to achieve delay, which greatly saves system resources

• The SysTick timer is bound to the NVIC interrupt to generate the SYSTICK interrupt (the interrupt number is 15)

The interrupt priority of SysTick can also be set

In Stm32F10xxxthe reference manual, the system tick calibration value is 9000. When the system tick clock is set to 9MHZ, which is the maximum value of HCLK/8, a reference of 1ms is generated.

CM3 provides two clock sources for SysTick

• The core's free-running clock FCLK (this is the HCLK clock)
  • Free table now does not come from system clock HCLK
  • FCLK continues to run even when the system clock is stopped
• External reference clock STCLK (this is generally HCLK, 1/8 of the AHB bus, 9MHZ)

SysTick tick timer, in FreeRTOSthe middle, is to use SysTick tick timer to promote task switching and time management

The configuration of SysTick in the firmware library is in the misc.cand core_cm3.hfile

• The clock source of SysTick is selected in misc.cthe file
• Initialize SysTick in core_cm3.hthe file

SysTick clock source
selection

Initialization of SysTick

Enable the SysTick interrupt, enable the SysTick interrupt, and the time interval of the SysTick interrupt

Simply put, the value of ticks is the value of relaod, the interrupt will be generated when val==0, and the two interrupts are the time when the value of val changes from reload to 0

Start from the initial value, count down, count to 0, generate an interrupt, and so on

Use SysTick to implement delay

Select the external clock HCLK, divided by eight, the clock is 9MHZ at this time

As we have said above,当系统滴答时钟设定为9MHZ，为HCLK/8的最大值时，产生1ms的基准

After the initialization is completed, the delay can be realized

Load the delay into the LOAD register, and clear the counter, wait for the time to arrive, close the counter, and clear the counter

Interval

Simply put, the value of ticks is the value of relaod, the interrupt will be generated when val==0, and the two interrupts are the time when the value of val changes from reload to 0

Start from the initial value, count down, count to 0, generate an interrupt, and so on

Use SysTick to implement delay

Select the external clock HCLK, divided by eight, the clock is 9MHZ at this time

After the initialization is completed, the delay can be realized

Load the delay into the LOAD register, and clear the counter, wait for the time to arrive, close the counter, and clear the counter