With the continuous increase of non-linear load users in the power grid
,
the problem of power quality is becoming more and more serious
.
The high-precision data acquisition system can provide power quality
Quantitative analysis provides accurate data support
,
which is the key basis for solving power quality problems
.
By comparing the design scheme of the existing high-speed acquisition system
,
the main
The control circuit mostly uses
ARM
microcontroller with
AD
conversion chip
,
ARM+DSP
with conversion chip and
FPGA+DSP
with
AD
conversion chip
The structure of the way
[1-5]
.
ARM
has good decision-making control characteristics
and
is widely used in the field of industrial control
,
but its data processing speed is slow
and
cannot meet
real-time performance of the system
.
Due to
the serial instruction stream nature of
DSP
, complex data processing can only be performed in low-speed systems . Fully Programmable FPGA
And the characteristics of parallel data processing make it more and more popular in the field of digital signal processing
,
but the decision-making ability of the system is weak
[6-10]
.
At the same time
,
ARM
and
DSP
,
FPGA
and
DSP are connected
through low-speed industrial communication interface
(SPI
,
Mcbsp,
etc.
)
or using processor external bus interface
The multi-chip structure
complicates
the board-level circuit design
, and
frequent communication between chips is difficult to ensure the stability of the system
[11-12]
.
In this regard
,
a
data acquisition system based on
ZYNQ is designed
. ZYNQ SOC integrates ARM dual-core cortext-A9 processor and Xilinx7
series
FPGA
architecture
.
On-chip integration of highly customized
AXI
interconnection and interface forms a bridge between the two parts
,
speeding up the communication between modules and
Enhanced system stability
.
Utilize the hardware programmable feature of
FPGA
to design
the interface controller connected with high-speed
AD
, call AXI_DMA
The official hard-core
IP
can directly transfer the collected data to
ARM
's
DDR
for storage
.
ARM
drives serial port or
HDIM
port to complete data display
Display
,
execute the overall decision of the system
.
After analyzing the power quality of a substation
,
it is found that the high-order harmonics of the power grid are about
60
times in the steady state
, and
the system chooses
The
AD7606
acquisition card has a sampling frequency of
200 kHz
,
8
-channel synchronous acquisition
, and
a resolution of
16
bits
.
The acquisition accuracy and speed can meet the requirements of data acquisition.
Integrates system design requirements
and
realizes analog-to-digital conversion of signals
.
Compared with
ZYNQ
's
built-in
XADC with
12 -bit width and 1 MHz sampling rate AD7606 has
Higher conversion precision
.
1
The overall design of the data acquisition system
Figure
1
is a schematic diagram of the overall design of the system
. The input terminal
of the AD7606
acquisition card leads to a
16
-pin interface
,
which is used for
8
channels to connect to external analog
VP
and
VN
of the signal line
.
The analog signal enters the
AD
acquisition chip
, and through the analog multiplexer input conversion circuit to complete the analog signal to digital
Word signal conversion
.
The system realizes the high-speed communication between AD7606 and ZYNQ
through the
40 -pin expansion port
. The interface is located in the PL part of ZYNQ , using
The interface controller program is written in Verilog
code to realize
the AD
acquisition control function and then packaged as
an IP
core
.
The main design includes
AD
reset
,
clock
, and
acquisition .
sample rate
,
chip select
,
FIFO
data buffer, and
AXI
protocol instantiation
.
Call
Xilinx
official
IP
core
AXI-DMA
to transfer
PL
data
to
PS
in
DDR memory
.
ARM
drives
the URAT
or
HDMI
port to transmit data to the terminal for display
.
The AD
controller first buffers the collected data
Stored
in
the FIFO
, read the data from the FIFO and convert it to the AXI-stream stream data format , which can speed up the data processing speed and reduce the data
According to the impact on the timing
,
the system uses
the AXI-stream register slice
module to improve the interface timing
.
The system adopts asynchronous timing design
,
ADC
configuration
The clock frequency is
50 MHz
,
the AXI
bus clock is
100 MHz
, and
the data display
clock is
150 MHz .
Setting the clock
can
effectively prevent the data overflow of the cache module
.
2
Hardware Design of Data Acquisition System
2.1
Introduction to ZYNQ
ZYNG
is a new generation
( all-programmable system-on-chip , SoC ) fully programmable system-on-chip launched by
Xilinx
. essential features
It is a combination of a dual-core
ARM Cortex-A9
processor
,
referred to as
PS
and a traditional field programmable gate array
(
field programmable
gate array
,
FPGA
)
logic components referred to as
PL
[13]
.
The chip integrates
AMBA AXI4
interconnection
,
internal memory
,
external memory and peripherals
.
peripherals
It mainly includes
USB
bus
,
Ethernet
,
SD
interface
,
UART
interface
,
HDMI
port
,
GPIO
port, etc.
[14-15]
.
Logic cells
with up to
6.25 MHz
And
the internal clock of
766 MHz
can realize hardware acceleration and scalability , fully satisfying the real-time and high precision of system design .
2.2 AD7606
controller design
AD7606
adopts
+5 V
single power supply
,
on-chip integrated input amplifier
,
overvoltage protection
,
second-order analog anti-aliasing filter
,
analog multiple
Multiplexer
,
16
-bit
200 kbps SAR ADC
and a digital filter
,
2.5 V
reference voltage buffer and high-speed serial port and parallel port
,
can
Realize
8-
channel simultaneous sampling
,
all channels are
sampled at a throughput rate of up to
200 kbps
[16] . The AD controller is shown in Figure 2 , and the external signal passes through
The ad_data[15
:
0]
port enters the
AD
controller
.
The unconnected ports are controlled by
Verilog
code programming
, and
the conversion process is designed according to the timing characteristics
.
8 channels are sampled synchronously when the rising edge of the ad_convstad
port signal starts
, and when the port ad_busy is high, it indicates that the signal is being converted . When the port
When the
ad_busy signal is a falling edge, it means that
the ad_rdd
read signal port can be started
, and
the controller can read
the collected data of 8 channels
in the data bus
.
The ad_cs
port controls data read chip selection
.
ad_os
is
the sampling rate selection port of the internal digital filter
of AD
, there are 8 kinds of rate options in total , the controller can
You can choose whether to
use the filter through this port
to achieve higher measurement accuracy
.
The system transfers the ADC acquisition data to DDR
through
DMA
Among them
,
the port
M00_AXIS[15:0]
is the data output channel interface
, and
the transmission data is streaming data
. It is necessary to convert
the ADC data to AX
during design
IS
flow data
.
Since the
ADC
clock
is different from the clock frequency of
AXIS
, it is necessary to add FIFO to the ADC for cross-clock domain processing and buffer
The role of
the
AXIS
clock frequency is twice
the ADC
clock
,
so data overflow will not occur
.
ARM
configures the
adc_clk
clock port
,
Adc_rst
and the reset terminal complete the acquisition timing and reset control
.
2.3
Acquisition System Communication
The system is divided into internal communication and external communication
.
The internal communication is carried out
through the
AX4 bus
, including 5 independent transmission channels for reading address and reading
Data
,
write address
,
write data
,
write reply
,
these channels support one-way transmission
,
including
AXI4
,
AXI-Stream
,
AXI-lite 3
interfaces
,
system data
Data
is transmitted in one direction from
AD
to
ZYNQ
; therefore only the write channel is enabled . The AXI-Stream interface adopted by DMA can directly communicate between master and slave devices .
The reading of row data
and
data transmission do not require addresses
,
which improves the real-time performance of the system
.
In the AXI
protocol, the master device and the slave device are established through a handshake signal
connect
.
As
shown in Figure
3
, the use of UART interface and external communication system uses Silicon Labs CP20102GM chip to realize USB interface conversion
The function of the UART
interface
,
and uses
the micro USB
line to communicate with the terminal serially
.
TX/RX signal of
UART
interface and
ZYNQ PS
The BANK501
signal is connected
,
the VCCMIO level of
BANK501 is
1.8 V , and the data level of CP2102GM is 3.3 V , and the middle of the system is connected to
TXSOQ02DCUR
level conversion chip realizes level matching
.
2.4 DDR
high-speed storage
Figure
4 is a schematic diagram
of
the hardware connection of DDR3
DRAM
. DDR is a double-rate synchronous dynamic random access memory .
Both rising and falling edges are sampled
,
effectively improving the storage rate
.
The system is equipped with two
4 Gbit
DDR3
chips
,
the
model is
H5TQ4G63ARFR-PBC
.
The bit width of the DDR
bus is
32 bits
, and
the maximum operating speed can reach
533 MHz
.
DDR3
memory directly communicates with
The BANK502 storage interface
of the
ZYNQ processor is connected . When the ZYNQ-Processing System core configures the memory , it must ensure that the DDR interface type
same or compatible
.
3
Software Design of Data Acquisition System
In the
Xilinx IDE suite
,
the hardware engineering design is completed
in
vivado
Based on the calculation
,
the SDK
will automatically configure some important parameters
,
divided into
For
3
modules
:
hardware definition
(
hardware definition
)
contains a fixed
Defined register types
, address maps, and
IP
included in the current design
Block confidence
;
board support package
(
board support package
)
contains support
Driver and variable parameter header files that support IP
blocks
; application
(
application
)
for testing different functions
.
Complete the system accordingly
Software part design
.
3.1 ADC-DMA
control
ADC-DMA
control is the core module of the system software
,
the program operation
Initialize
the ADC
and
DMA related parameters
before the line , such as
ADC
base address
,
offset address
,
acquisition length
,
coefficient
,
byte
number
,
number of bits, and number of channels
.
DMA
maximum transfer bytes
,
device
ID
,
Interrupt
ID
and interrupt trigger source
.
ADC
data is written into
FIFO
is
Stored in the order of
1
to
8 channels
, the program defines a two-dimensional array ,
Separate the data of each channel
and
adjust the order of the channels
.
In order to display all channel data on the screen
,
the system converts each channel
The coefficients are fine-tuned
to
make the waveforms of each channel misaligned
.
DMA
The interrupt trigger type of is complete trigger
,
this interrupt belongs
to
ZYNQ
Shared interrupt
,
the trigger mechanism is triggered when the task execution is completed
,
hard
In the software design,
the DMA
only opens the write channel interface
, and
the interrupt function only
Open
Streams
to
Memery Map
interrupts
.
SDK Terminal
After configuring the interface
, baud rate and data bits
, use the printf function to drive
The dynamic serial port communication completes the terminal data display
.
at the same time through
The HDMI
interface is connected to the display
to
realize the real-time display of the waveform
.
The ADC
control flow chart is shown in Figure
5
.
3.2 DMA-SG
mode application design
The DMA-SG
mode has more efficient data transfer characteristics than the simple mode
,
allowing a single
DMA
transfer to access multiple memory spaces
,
The interrupt is triggered after all tasks are completed
.
After the hardware project turns on
the SG
mode
,
the M_AXI_SG
interface
is used to read and write the linked list . The linked list is sent in 13
The descriptor composed of registers is the basic unit
.
The descriptor contains the next descriptor pointer address
,
data cache address
,
control storage information, and so on
.
Write
The channel
SG
mode drive design process
is shown in Figure
6
, which requires opening up a cache space in the memory and making a linked list . Write the first descriptor to the current
address register
.
Start
DMA
and set up an interrupt system
,
which will trigger an interrupt after the transfer is over
.
Write the last descriptor to the end register
,
triggering
The DMA
grabs the linked list descriptor through the bus
, and
reads the next descriptor after
the BD packet transmission is completed
. Make the last descriptor pointer point only to the first
The address
of a descriptor
matching the loopback mode
.
After the data processing is completed
,
the state of the linked list is cleared
.
3.3
display control module
The module provides an easy-to-use
API
to control the display
connected to the system development board
via
VGA
or
HDMI
. According to the display
Rate Size sets the canvas size
,
background and color
.
Take a rectangular section in the canvas to display the amplitude and propagation time of the waveform
.
In-interval design
32
×
A small square of
32 pixels is used as the quantization unit
, displayed every
4 pixels
in the horizontal and vertical directions
, the grid is displayed in gray , and the background is displayed as
black
.
The grid superposition function and waveform superposition function are designed to read the data in the canvas buffer area in real time
to
realize uninterrupted display of waveforms
.
The data read in Catch
is displayed as discrete points on the image
,
compare the data with the previous data
,
get the difference and draw points in the same column
,
so that
The waveform display is smoother
.
The size of the waveform area can be changed by modifying the waveform start position parameter
,
but the column start position plus the waveform height must be
It must be smaller than the display resolution
,
otherwise it cannot be displayed normally
.
The system screen uses color bars as the display background
, and
a seamless frame buffer area is designed
to
realize
Seamless animation
.
The image driving process
is shown in Figure
7
. First, create a display object and initialize it . Call DisplaySetMode function to set
Set the transfer mode
.
Call
the DisplayStart
function to transfer data to the display
.
To achieve seamless animation
,
an image needs to be drawn to the current
Call the DisplayChangFrame function to display the frame buffer area that has not been displayed before
,
and repeat the operation to display the image . If you change the resolution , you need to call the display
The display mode function sets the mode
,
and then
starts
transferring data from the beginning
.
4
Analysis of results
Using
digilent
's
Analog Discovery 2
arbitrary function generator to provide the required signal for experiments
.
Figure
8
(
a
)
is a signal generator set
Set the page
, the experiment
collects and displays
the sine signal
,
20 kHz
, and
2 V signal
, the AD sampling frequency is 200 kHz , and all 8 acquisition channels are turned on .
Due to hardware constraints
,
only single-channel experiments were performed
.
The HDMI
display results and the test platform
are shown in Figure
8
(
b
)
, and the graphical interface shows the positive
The sine wave is the signal collected by the system
.
For longitudinal analysis
,
the distance between adjacent dotted lines represents a measurement unit
, and
a total of
4 units are represented from the peak to the trough.
From
+2 V
to
-2 V
signal
,
the analysis shows that the experimental result is the same as the original signal waveform
.
In order to further verify the acquisition accuracy
,
an
8-
pass
Test of
4
analog voltage values
,
the test results are printed out through the serial port
,
as
shown in Table
1
, the reference voltage in the first column is sent by the signal generator
value
,
and the last
8 columns
are system measurement results
.
According to formula
(
1
),
the acquisition error is calculated to be
0.02%
.
For the high-speed data acquisition requirements in the field of power quality detection
, the
Vivado development kit provided by Xilinx
is used
to complete it on the ZYNQ SoC
Design of high-speed data acquisition system
.
In terms of hardware
, this design
uses
the FPGA part of
ZYNQ to realize the acquisition control of the system
, and the ARM part
Complete data transmission
,
storage and result display
, among which
the acquisition control of AD7606 is realized
based on the custom
ad7606_sample IP
, using AXI
HP
high-speed interface
,
AXI-DMA
hard core
IP
, and
DMA-SG
mode speed up the data transmission and processing speed of the system
.
On the software side
,
complete
the SG
BD
package creation
,
waveform display design and
DMA
data transmission control
in the mode
.
Experimental results through testing show
that
the ARM
side drives
the HDMI
The interface realizes real-time online display of collected signals
.
By analyzing the data printed by the serial port terminal
,
it is determined that the acquisition error of the system can be
up to
0.02%
.
The system has the characteristics of small size
,
low power consumption
,
high precision
,
strong real-time performance
, and
strong stability
.