s3c2440 bare Programming - Programming clock (a, presentation system clock 2440)

1. bus frame

The figure is a bus frame 2440, which AHB (Advanced High performance Bus) high-speed bus, APB (Advanced Peripheral Bus) peripheral bus.

Different bus corresponding to a different clock.

SOC <-> FCLK
AHB <-> HCLK    
APB <-> PCLK 

among them:

1. Use the AHB bus are: LCD controller, usb controller, interrupt controller, memory controller and so on ...

2. APB bus are: i2c, spi, timer, gpio, adc, etc ... Specifically FIG.

2. Clock frame

The following figure shows a block diagram of a clock of 2440 Soc:

Here to explain the system clock from the details:

1. How to choose a clock source:

s3c2440 has two clock sources, the OSC is one, a is EXTCLK external clock, the clock marked above block diagram, of course, we can also see the manual "Figure 7-1. Clock Generator Block Diagram".

So how to choose OSC or EXTCLK is it?

Open schematics, pin grounded OM3, OM2, then OM [3,2] = 00. Therefore, according to the manual "Table 7-1. Clock Source Selection at Boot-Up" shows the crystal clock source for the OSC.

2. How to get HCLK, PCLK, UCLK?

First understand PLL, DIV

PLL:用锁相环进行倍频
DIV:用分频器进行分频

As shown below:

Generated MPLL (Main PLL) and UPLL (USB PLL), MPLL of FCLK directly to, by dividing HDIVN to HCLK, PCLK by PDIVN to divide, then pass below the respective devices.

osc after UPLL (USB PLL) get UCLK.

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Origin www.cnblogs.com/fuzidage/p/12001237.html