Wei Dongshan ARM bare metal and uboot encyclopedia (1st enhanced version) study notes 10-Lesson 010_Master the ARM chip clock system

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①AHB bus (H-High): high-speed bus; clock: HCLK
APB bus (P-peripheral): low-speed bus, low-speed peripheral bus; clock: PCLK
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Remarks:
① An external reset chip is required due to unstable power supply when power is first applied Real-time monitoring of the power supply status,
when the power supply conditions are not met, the nReset pin is set to 0;
when the power supply conditions are met, the nReset pin is set to 1 to release the CPU. ②According to
the value of the configuration pin, FCLK=crystal oscillator;
③When the nReset pin is released, the CPU starts to run, the value of the external configuration pin stored in the PLL ④Set the
PLL, at this time FCLK stops, the CPU stops
⑤Set PLL is completed, PLL works
⑥FCLK =New clock output by PLL setting

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Programming realization:

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Note: The manual requires HDIVN! When =0, the CPU bus needs to be modified from fast mode to asynchronous mode.

mrc
//c表示co-processor
//r表示reg
//m表示move
//把数据从协处理器移到寄存器

mcr
//把数据从寄存器移到寄存器

Actual code:

	/* 设置MPLL, FCLK : HCLK : PCLK = 400m : 100m : 50m */
	/* LOCKTIME(0x4C000000) = 0xFFFFFFFF */
	ldr r0, =0x4C000000
	ldr r1, =0xFFFFFFFF
	str r1, [r0]

	/* CLKDIVN(0x4C000014) = 0X5, tFCLK:tHCLK:tPCLK = 1:4:8  */
	ldr r0, =0x4C000014
	ldr r1, =0x5
	str r1, [r0]

	/* 设置CPU工作于异步模式 */
	mrc p15,0,r0,c1,c0,0
	orr r0,r0,#0xc0000000   //R1_nF:OR:R1_iA
	mcr p15,0,r0,c1,c0,0

	/* 设置MPLLCON(0x4C000004) = (92<<12)|(1<<4)|(1<<0) 
	 *  m = MDIV+8 = 92+8=100
	 *  p = PDIV+2 = 1+2 = 3
	 *  s = SDIV = 1
	 *  FCLK = 2*m*Fin/(p*2^s) = 2*100*12/(3*2^1)=400M
	 */
	ldr r0, =0x4C000004
	ldr r1, =(92<<12)|(1<<4)|(1<<0)
	str r1, [r0]
	/* 一旦设置PLL, 就会锁定lock time直到PLL输出稳定
	 * 然后CPU工作于新的频率FCLK
	 */

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Origin blog.csdn.net/xiaoaojianghu09/article/details/104343920