Both RAM and DDR can directly interact with the CPU (because the data processing speed is fast enough). The programs we burn into the development board will eventually be loaded into DDR or RAM, and the CPU will read data and instructions from DDR or RAM.
RAM: A section of available memory inside the CPU . The range is 0x00900000~0x0091FFFF, and the size is 128 KB
DDR: The memory outside the CPU , encapsulated in the SOC, the size of DDR is 256M or 512M. If the DDR size is 256MB, then the range is 0x80000000~0x90000000.
Table of contents
1. ROM and RAM
1、ROM
Read-only memory, similar to a computer hard disk, does not lose data after power failure, and is suitable for storing data, such as audio, video, pictures and other information. It can also be called Flash, such as EMMC, UFS, and NAND Flash are actually ROMs.
- Data will not be lost after power failure
- IO speed is slower compared to RAM
- The capacity is generally larger (IMX.6ULL has 512 MB of NAND Flash or 8 GB of EMMC )
2、RAM
Random access memory is similar to the running memory of a computer. Data will be lost after power failure. It is generally used to save program data and intermediate results. For example, the SRAM, SDRAM, and DDR introduced later are actually RAM.
- Data loss after power failure
- IO is fast and can directly interact with the CPU
- Smaller capacity (256 MB or 512 MB for DDR3 on IMX.6ULL)
2. RAM
Subsequent SDRAM and DDR are actually improved step by step on the basis of the previous one, so we need to understand in turn what improvements have been made in SRAM - SDRAM - DDR - DDR2 / DDR3.
1、SRAM
Here we take 16-bit wide (16-bit data) and 1 MB SRAM as an example. Assuming that the SRAM wants to obtain data, then it needs to know which address to go to, how much data to fetch at a time, whether to read data or write data . This sentence contains the functions of the following three lines.
① Address line
There are 19 address lines (A0 ~ A18), then the accessible address size is 2^19 = 524288 = 512KB.
② Data cable
There are 16 data lines in a 16-bit width, corresponding to 16 bits, which is equivalent to accessing 2 bytes of data every time you go to a certain address, so there are high and low bytes, among which IO0~IO7 are low bytes, IO8~IO15 are high bytes.
This also verifies that the size of SRAM = the number of accessible addresses × the number of bytes that can be obtained for each access address
= 512 KB × 2 = 1024 KB = 1MB
③ Control line
When accessing a certain address, whether to read data or write data, if it is to read data, read the high byte first or read the low byte first, these are all done by the control line.
- CS1, CS2: Some systems may have multiple SRAMs, which one to use is determined by CSx
- OE: output enable. Active low, master reads data from SRAM
- WE: Write enable. Active low, master writes data to SRAM
- UB: read high byte data
- LB: read low byte data
2、SDRAM
The disadvantages of SRAM are high cost and small capacity. In fact, the demand for memory is getting higher and higher, and a solution for large memory is needed. Finally, SDRAM came into being. SDRAM (Synchronous Dynamic Random Access Memory), synchronous dynamic random access memory, since it is "synchronous", it means that a clock line is needed; "dynamic" means that it is constantly refreshed to ensure that data will not be lost. The difference between SDRAM and SRAM is:
- A clock line is introduced to refresh data synchronously
- Multiple BANKs reduce address conflicts and improve memory access efficiency
- Addressing by row and column in each BANK
Which address of which bank to go to, how much data to access, whether to read data or write data . Below is a 16-bit wide, 32MB SDRAM with a speed of 133MHz, 166MHz or 200MHz
④ BANK selection line
A single BANK will cause serious addressing conflicts and reduce memory access efficiency. Therefore, there are multiple BANKs now, but the specific BANK to get data depends on the BANK selection line BS0, BS1
③ Address line (A0~A12)
SDRAM is addressed through rows and columns. The row address and column address are controlled by the same line. How does SDRAM know whether the currently received address is a row address or a column address? This needs to rely on the RAS and CAS contained in ① in the figure. RAS is a row strobe signal, and the low level is effective. If RAS is low , it means that A10 is the row address at this time ; if CAS is low , it means this When A10 is the column address .
Take the W9825G6KH model as an example, A0~A8 is the column address, a total of 9 bits; A0~A12 is a row address, a total of 13 bits. So addressing range: 2^9 × 2^13 = 4MB. According to ⑥ in the figure, it can be seen that the data width is 16 bits, that is to say, 2 bytes can be accessed each time.
Therefore, the size of a BANK = 4MB × 2 = 8 MB
② A10 (address selection line)
In addition to being a member of the address line, A10 also controls "precharge". "Precharge" refers to the operation of closing the current row and preparing to open a new row, so that a new address can be accessed.
⑤ BANK block
A single BANK will cause serious addressing conflicts and reduce memory access efficiency. Therefore, there are multiple BANKs now, and the data sheet of each SDRAM will indicate how many BANKs there are. The SDRAM shown in the figure has 4 BANKs.
Knowing from the address line that a BANK is 8MB, then the size of SDRAM = 4 × 8MB = 32 MB
① Control line
Similar to SRAM, only the differences from SRAM are introduced here
- CLK: clock line
- CKE: clock enable
- RAS: Row strobe signal, active low. When low level, it means that A0~A12 send the row address
- CAS: column strobe signal, active low. When low level, it means that A0~A8 send column address
3、DDR SDRAM
SDRAM solves the problem of small SRAM memory, but people have a new demand, that is, the speed is not fast enough, so there is the current DDR. DDR (Double Data Rate SDRAM), double rate SDRAM, the "double" here comes from the improvement of the clock, SDRAM transmits data once in one clock cycle, but DDR transmits data twice in one clock cycle (rising edge and falling edge respectively pass the data once).
The original SDRAM transmission speed is 133~200 MT/s, MT/s means how many megabytes of data transmission per second. The transmission speed of DDR becomes 266~400 MT/s.
4、DDR2 / DDR3 / DDR3L
The transmission speed of DDR has been further improved, and there are now DDR2, DDR3, and even DDR4. DDR2 further increases prefetch on the basis of DDR (equivalent to transferring data 4 times in one clock cycle)
- DDR2：533~800 MT/s
- DDR3：1066~1600 MT/s
In order to adapt to different scenarios, DDR3 has derived many different models, such as LPDDR3 and DDR3L. The difference between them is the working voltage.
- DDR3: Operating voltage 1.5 V (desktop)
- LPDDR3: Operating voltage 1.2 V
- DDR3L: working voltage 1.35 V (general mobile phone, embedded, notebook)