Clock Control Module
core
4 levels to configure the chip clock
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Crystal Clock
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PLL and PFD clock
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PLL selection clock
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Root Clock/Peripheral Clock
System clock source
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RTC clock source: 32.768KHz
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System clock: 24MHz, used as the main crystal oscillator of the chip
PLL and PFD multiplied clock
7 phase-locked loop circuits (each phase-locked loop circuit can multiply the frequency of the clock)
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ARM_PLL: drives the ARM core
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528_PLL: The frequency is fixed at 528MHZ, the multiplier parameter is fixed at 22, and the system bus clock
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USB1_PLL: drives the first USB physical layer
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AUDIO_PLL: drive audio interface
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VIDEO_PLL: drive video interface
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ENET_PLL: drives the external Ethernet interface
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USB2_PLL: drives the second USB physical layer
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10.3.1 Centralized components of clock management system
18.6 CCM Memory Map/Register Definition
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CCM_ANALOG_PLL_XXX
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Set the main frequency of the PPL clock (pll1_main_clk)
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Enable PLL clock output
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CCM_ANALOG_PFD_XXX
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Set the frequency division coefficient of PFD under PPL
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PLL selection clock
Select the output of PLL1 and PLL3, divide the frequency of PLL4 and PLL5
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The cpu core clock comes from the PLL1 clock.
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When the power is first turned on, the PLL1 clock is not initialized, and the arm core first uses the 24M crystal oscillator frequency, and then switches back to the PLL1 clock after the PLL1 clock is output stably.
CCM_CCSR: Select pll1_sw_clk, step_clk clock source
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The step_clk clock source is set to 24M crystal oscillator
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pll1_main_clk clock source is set to step_clk or pll1_main_clk
18.5.1.5.1 Clock Switcher
peripheral clock
Set the clock source for the peripheral. There are multiple options for the peripheral clock source:
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The ladder icon indicates the configuration of the upper-level clock source
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The square icon indicates the frequency division factor
The associated register is indicated next to the icon
18.3 CCM Clock Tree