A Study of Routing Algorithms for PCB Design
Chapter One
introduction
Chapter main printed circuit board (PCB) routing algorithm design, and presents three main problems associated with the PCB layout. This section begins with an overview of the architecture and structure of the package and PCB redistribution layer (RDL), and then three typical wiring problems in the PCB, and suggestions herein.
1.1 PCB and Flip-chip Overview
PCB is a plate made of glass fiber, epoxy resin, or other material, may be provided traces, pads, and other functions to connect electronic components. It is used in almost all electronic products, and plays a very important role. In a recent PCB design, due to the rapid development of integrated circuit technology, the increasing complexity of the PCB. Such a high pin density such that the PCB layout is very error-prone and time-consuming [1]. Therefore, recent research has focused on various PCB layout issues. In order to accurately understand the PCB layout issues This section starts with some basic knowledge of the PCB.
PCB structure
in modern PCB design, it usually contains a plurality of components, such as a multi-chip module (the MCM), memory, and I / O module [2]. These components, as a set of pins dense array mounted on a board, shown in Figure 1.1. The array of pins to be connected by line segments do not intersect.
The number of layers of the circuit board, PCB, there are three types: single-sided, double-sided and multilayer, shown in Figure 1.2
A single panel
on one board, the wiring concentration on only one side, FIG. 1.2 (a) shown in FIG. Because many the wiring design strictly limited, for example, the line can not cross each plate, one surface of the wiring board thus usually fail. In addition, modern high-density wiring design of the wiring pins into a single double-sided more and more difficult. Therefore, only the circuits using this early type of circuit board.
Double panel
with a different single panel, the panel has a double line on both sides, as shown in 1.2 (b) shown in FIG. It is a two-layer board, conductors of different layers are connected by vias. These are usually referred to as through-hole vias, metal coated thereon. Due to the large area of the double-sided wiring board, and the wiring conductors may be indifferently through the through hole, and therefore the double-sided circuit board may be single-sided circuit board to solve the cross wires, routing problems such as limited resources. It is typically used in more complex circuits.
Multilayer
multilayer using more single-panel or double-panel to increase the available area, as shown in 1.2 (c) shown in FIG. All the outer and inner layers can be used for routing. The same double-sided, multi-layer board using vias to connect the conductor to the different layers. In the current application, the most common PCB having 4-10 layers. Multilayer assembly and allows for higher pin density.
In recent years, due to the increased number of pins and strict design rules, typically between the pin arrays and of different internal components [2], the routing resources are limited to the components. Thus, a multilayer PCB board is widely used. In this paper, we study on PCB layout design also involves multiple layers.
Flip-chip structure
in PCB fabrication, assembly should be packaged on the board. Due to the shorter wire connection can produce higher circuit performance, there is a packaging technology, the chip can be mounted directly to the plate to the other conductor connector [3]. This technique is called bare chip package, comprising three modes: wire bonding (wire bonding), the bonding tape (tape-automated bonding) and flip chip (flip-chip).
Wire bonding
a wire bonding device is a method of manufacturing the substrate during interconnected so that, in FIG. 1.3 (a) shown in FIG. It is a major technical package assembly between the PCB electrically connected with the circuit board. In wire bonding, the chip is installed upright, the lead assembly for interconnecting the outer conductor to [4]. Wire bonding the bonding process is fast, excellent electrical and chemical properties, is considered to be a flexible and cost-effective interconnection technique. Most packages are PCB using this technique.
Tape bonding
(TAB) is obtained by using the etched copper beams placed directly into the chip during the PCB, FIG. 1.3 (b) shown in FIG. One end of the beam etched copper lead conductor, and the other end led PCB [5]. TAB is created as an alternative to wire bonding, and has been widely used in the display driver circuit. TAB has some advantages, such as smaller pads, forming fewer and lower cost. Further, it improves the heat transfer, the high-frequency execution, and require less surface area of the PCB [6].
Flip chip
flip-chip method is a buffer member to the outer conductor interconnect utilization. The active face of the flip chip structure shown in Figure 1.3 ©, and the chip is mounted in [7] on a substrate. Convex irregularities is placed on top of the ball chip pad. Flip chip pads so as to match the board are aligned for connection.
Flip chip structure can be divided into two types: peripheral I / O flip chip area and I / O flip chip, Figure 1.4 [8]. In the peripheral I / O flip chips, I / O pad is placed along the border of the die and the I / O pad should be routed to the ball inside the boundary. In the I / O area of a flip chip, I / O pad is placed in the entire area of the flip chip package. Compared with the peripheral I / O flip chip, the area of I / O flip chip may produce a shorter line length and smaller package sizes, so it has been more widely used.
Compared with conventional packaging technology, flip chip has many advantages: higher I / O density, higher throughput, better heat dissipation, interconnected shorter, smaller footprint, a smaller form factor and many more. These advantages make the modern flip-chip technology has become one of the most attractive design PCB [9].
Redistribution layer
While flip chip technology has been widely used in PCB design, but sometimes the position of I / O pads can not map well to the bump ball [10]. The results, shown in Figure 1.5, the RDL for the I / O pads to redistribute the bump ball, without changing the position of the I / O pads, the RDL for the metal I / O pad redistribution to the boss Penalties on. Irregularities ball on the RDL, for connection to I / O pad. In RDL by the prior art, the wire may be 90 degrees or 45 degrees by the line wirings.
The I / O pads may be redistributed to provide a higher density, greater flexibility and lower cost, and improve circuit performance penalty convex. Further, in certain applications, it is an effective and efficient power and ground contacts off-chip connection method of conversion. Board-level chip scale to scale.
Recently, due to the increased mass flip chip package I / O pads, RDL may not be sufficient to complete only a single wiring. Further, wiring may be drawn out in a single longer length of wire in the RDL. Thus, in some studies have considered RDL for connection between a plurality of I / O pads and bumper balls [12]. In this article, we refer to a single and multiple RDL RDL study flip-chip design.
1.2 typical routing problem
, we will discuss the problems in the PCB layout based on the basic principle of this section above the PCB. Modern PCB generally comprises several chip package, the package is a pin array, we do not cross purpose is to generate network cabling [1]. It describes three typical PCB wiring problem: escape wiring, river, and the wiring line RDL.
Escape wiring
Escape wiring is a wiring problem between the inner pin array assembly. As shown in Figure 1.6, is an array of pins from the pin to the internal routing boundary, like the pin to assist the pin escape sequence.
The main task is to use the escape wiring layer as little as possible to escape a group of pins, because it usually dominates. In addition, sometimes it should be provided in order to match the boundary pins of the two components, for subsequent wiring river. Escape route There are three main types of problems: unordered escape wiring, and the wiring ordered escape escape while the wiring [1], which are used in PCB routing, but not discussed herein.
River wiring
with respect to the escape wiring, routing wiring River problem between two or more components, which is connected to the assembly pin escape boundary limit having a length, shown in Figure 1.7. Typically, the obstacle is aware of the problems in the river.
The main task is to link River wiring length within the constraints of the pin to maintain the escape of the wiring plane generated topology. There are two typical wiring River categories: minimum - maximum wiring length of the wiring length and the like. Minimum - maximum line length, the length of each line should meet a given minimum and maximum length. Purposes wiring length is to produce a wire having the same length.
In recent PCB design, since high integration, the signal propagation delay or skew has become an important factor of circuit performance. We can control the signal propagation delay by adjusting the length of the wire. If the routing area is large enough, the control network cable length is difficult. However, the routing area is usually limited, and a plurality of networks should be considered in a dense area. Therefore, how to balance multiple network lines long become a very difficult problem. In addition, wiring problems River, usually fixed to the position of the pin member, and typically the starting and target pins disorder. Thus, the multilayer wiring is used for unordered pin, and the actual problem is how to allocate these pins and the wiring layers thereof in any order.
RDL wiring
Further, as the special structure of the flip chip, the wiring RDL is also often discussed in the PCB design. It is connected to the I / O pads by minimizing the line length of the convex spherical. There are two main RDL routing problems. One problem is that free distribution wiring problems, which are not assigned to any I / O pads to ball irregularities before any wiring. Another problem is the problem of pre-assigned route. In this issue, prior to the wiring connection between the defined I / O pads and bump ball. Since the pre-allocated connection has more routing constraints, as compared with the free distribution of pre-allocation routing problem much more difficult.
For RDL wiring problems before flip-chip dispensing area, generally focused on how to allocate I / O pad to the solder bump and minimize bus length. Further, since it is difficult with the recent conventional 2D IC interconnects solve some problems have become so good 3D IC for high performance circuits. Thus, it should be addressed I / O pad allocation in the 2D and 3D IC RDL wiring problems and to improve the performance of the entire circuit.
1.3 Research Program
Aiming PCB design a series of routing algorithms to solve these different problems. This article includes the following three points.
First, in order to pin assignments disorderly wiring layer and obtain the results of equal length, the routing algorithm is proposed which can identify the area in the PCB design. During dispensing layer, the layer is determined using the pin between the start and destination sets of pins longest common subsequence (LCS) algorithm. In the routing process, if the pin is not satisfied sequence relay routing topology conditions, the need to set up a virtual boundary. Basic line multi-network is generated by a single flow process. Further, taking into account the target region and the wiring length requirement coefficient using R-flip and C-flip technique to adjust the line length. The proposed routing algorithm to obtain a long wire having a better balance in a reasonable time and less CPU worst incorrect wiring length.
Secondly, for the minimum length of the bus, a new I / O pad allocation and ordering non Manhattan routing algorithm based on RDL, an area I / O flip chip designs. By the Manhattan distance between the I / O pads and bumps ball sorting, and amendments may be pre-assigned to determine the initial allocation. They were carried out to shorten the line length, and avoiding the release of three kinds of overlapping intersecting pairwise exchange procedure, in order to improve the initial allocation. Exchange order is the Manhattan distance between the I / O pads and bumps on the ball in accordance with the allocation decreasing. In order to shorten the wire length, wire having a non Manhattan RDL 90 and 45 degrees to connect the wire segment I / O pad and a bump ball. In addition, some non-routing and rerouting the connection should be disconnected. The proposed approach can effectively reduce the bus length. Regardless of I / O pads of the package size and location, the wiring capacity can be improved.
Finally, the above sorting method is applied to the same I / O pad allocation method and a wiring RDL 3D IC design. Similarly, we sorted by the Manhattan distance between two RDLsto and micro bumps, the same number assigned to the I / O pads. In order to shorten wire length, modified considering pairwise exchange between the wiring and cabling two monolayers were performed in RDL. Finally, some connections are not torn wiring and re-wiring. This method can also be used for 3D IC obtain routing bus in a shorter length, thereby reducing the CPU time.
In summary, the use of the proposed routing algorithm can solve the problems as long as the wiring and cabling problems RDL flip chip pins disorder PCB design, in addition, number of optimization, such as better line balance long, smaller worst-length error and using them can realize shorter length of the bus.
1.4 Thesis organization
remainder of this article is organized as follows:
Chapter 2 reviews the basics of PCB routing. First, it explains the four types of signaling network by the problem. Then, we discuss two basic methods and wirings representative of algorithms.
Chapter 3 describes the distribution layer and the sensing region as long as the wiring designing method of disordered PCB pin. By using the algorithm, it can be obtained and a better balance line length less the length of the worst bad routing.
Chapter 4 describes the routing I / O pad allocation and non RDL Manhattan wiring method based on sorting, an area I / O flip chip designs. The proposed method can be obtained within a reasonable short diameter CPU time .
Chapter 5 on the basis of the sorting method in Chapter 4 on the I / O pad allocation and routing method is applied RDL 3D IC. By comparison with other design methods, may further reduce the overall length of the wire.
Chapter VI of this paper are summarized and discussed future work.
