GD32F30x and GD32F403 series hardware are for reference.
1. Hardware design
1. Power supply
2. Reset
Notice:
1. The internal pull-up resistor is 40kΩ, and the external pull-up resistor is recommended to be 10kΩ, so that the voltage interference will not cause the chip to work abnormally;
2. If the influence of static electricity is considered, an ESD protection diode can be placed at the NRST pin;
3. Although there is a hardware POR circuit inside the MCU, it is recommended to add an external NRST reset resistance-capacitance circuit;
4. If the MCU starts abnormally (due to voltage fluctuations, etc.), the capacitance value of NRST to ground can be appropriately increased to lengthen the MCU reset completion time and avoid the power-on abnormal timing area.
3. clock
GD32F30x/GD32F403 series has a complete internal clock system, you can choose the appropriate clock source according to different applications, the main features of the clock:
4-32MHz external high-speed crystal oscillator (HXTAL);
8MHz internal high-speed RC oscillator (IRC8M);
32.768KHz external low-speed crystal oscillator (LXTAL);
48 MHz internal high-speed RC oscillator (IRC48M);
40kHz internal low-speed RC oscillator (IRC40K);
The PLL clock source can be selected from HXTAL, IRC8M or IRC48M;
HXTAL clock can be monitored;
The clock tree is as follows:
4. Start configuration
GD32F30x/GD32F403 series provide three startup methods, which can be configured through BOOT0 and BOOT1.
Users can configure BOOT0 and BOOT1 for power-on reset or system reset to determine the boot options. When designing the circuit, when running the user program, BOOT0 cannot be suspended. It is recommended to pass a 10kΩ resistor to GND; to run the System Memory for program update, you need to connect BOOT0 to high and BOOT1 to low. After the update is completed, connect BOOT0 to low to power on. User program; SRAM execution program is mostly used in debugging state.
The embedded Bootloader is stored in the system storage space and is used to reprogram the FLASH memory. In GD32F305xx/ GD32F307xx/ GD32F403xx devices, the Bootloader can interact with the outside world through USART0 (PA9 and PA10), USART1 (PD5 and PD6), USBFS (PA9, PA11 and PA12). In GD32F303xx (Flash<512kB) devices, Bootloader can interact with the outside world through USART0 (PA9 and PA10), in GD32F303xx (Flash>512kB) devices, Bootloader can communicate with the outside world through USART0 (PA9 and PA10) USART1 (PA2 and PA3) interact.
5. Download and debug
GD32F30x/GD32F403 series core supports JTAG debugging interface and SWD interface. The JTAG interface standard is a 20-pin interface, including 5 signal interfaces, and the SWD interface standard is a 5-pin interface, including 2 signal interfaces.
Note: After reset, the debugging related port is input PU/PD mode, where:
PA15: JTDI is pull-up mode;
PA14: JTCK / SWCLK is pull-down mode;
PA13: JTMS/SWDIO is pull-up mode;
PB4: NJTRST is pull-up mode;
PB3: JTDO is in floating mode.
There are several ways to improve the reliability of SWD download and debug communication, and enhance the anti-interference ability of download and debug.
1. Shorten the length of the two signal lines of SWD, preferably within 15cm;
2. Twist the two wires of SWD and the GND wire and twist them together;
3. Connect the two signal lines of SWD to the ground with a small capacitor of tens of pF;
4. Any IO of the two signal lines of SWD is connected in series with a 100Ω~1KΩ resistor.
6. Typical peripherals
ubs peripheral circuit
2. PCB Layout
1. Power supply decoupling capacitor
The GD32F30x/GD32F403 series power supply has four power supply pins of VDD, VDDA, VREF+ and VBAT. The 100nF decoupling capacitor can be made of ceramics , and it needs to be located as close as possible to the power supply pin . The power supply line should try to pass through the capacitor and then reach the MCU power supply pin . It is recommended to lay out Via near the capacitor PAD.
2. Clock circuit
GD32F30x/GD32F403 series clocks have HXTAL and LXTAL. It is required that the clock circuit (including crystal or crystal oscillator and capacitor) be placed close to the MCU clock pin, and the clock trace should be wrapped by GND as much as possible .
Notice:
1. The crystal should be as close to the MCU clock pin as possible, and the matching capacitor should be as close as possible to the crystal;
2. The entire circuit should be on the same layer as the MCU as much as possible, and the wiring should not pass through the layer as much as possible;
3. The PCB area of the clock circuit should be kept empty as much as possible, and no traces irrelevant to the clock should be taken ;
4. Keep high-power, strong interference risk devices and high-speed wiring as far away as possible from the clock crystal circuit;
5. The clock line is covered with ground to play a shielding effect .
3. Reset circuit
Note: The resistance and capacitance of the reset circuit should be as close as possible to the MCU NRST pin, and the NRST wiring should be kept away from strong interference risk devices and high-speed wiring, etc. If conditions permit, it is best to cover the NRST wiring to achieve Better shielding effect.
4. USB circuit
The USB module has two differential signal lines, DM and DP . It is recommended that the PCB traces require a characteristic impedance of 90ohm . The differential traces should be run in strict accordance with the rule of equal length and equidistance, and try to keep the traces as short as possible. If the two differential lines are not equal in length , the short line can be compensated with a serpentine line at the terminal.
Due to impedance matching considerations , the series matching resistance is recommended to be around 50Ω. When the USB terminal interface is far away from the MCU, it is necessary to appropriately increase the value of the series resistance.
Notice:
1. Arrange the layout reasonably to shorten the differential wiring distance ;
2. Draw differential lines first, try not to exceed two pairs of vias on a pair of differential lines , and place them symmetrically;
3. Symmetrical parallel routing to ensure that the two wires are tightly coupled , avoiding 90°, arc or 45° routing;
4. The RC, EMC and other devices connected to the differential traces, or test points, should also be symmetrical .
For the USB HS module, the data line and signal control line between the MCU and the external HS PHY should be kept as short as possible, and serpentine lines should be used for equal length processing. The precautions are as follows :
1. The layout should be placed reasonably , and the distance between the USB HS-PHY chip and the MCU should be as compact as possible ;
2. When wiring, aim at the length of the longest signal line , and compensate the other signal lines through serpentine routing .
5. BGA routing
The GD32F403x series includes BGA100 packages, and the corresponding model is GD32F403VxH6. The wiring of this chip is similar to that of other BGA chips. Firstly, each ball pad is fanned out, and then the wiring operation is performed . For the BGA package with 0.5 mm Pitch, if the BGA pad size is set to 0.25/0.35 , the distance between the via hole and the pad and the line width and line spacing are 3 mil, the Dog bone fan-out can be used, and the fan-out is shown in Figure 3- 5. As shown in the fan-out mode of the BGA100 package, the distance between the via hole and the pad is 4.5mil ; however, this kind of wiring has high requirements for the PCB manufacturer's process, and it is necessary to communicate with the PCB manufacturer before wiring . If the requirements are not met , the BGA package can be drilled with holes and blind buried holes
reference:
https://gd32mcu.com/cn/download/10?kw=