Principles of computer composition: 3. System bus

$experience\huge{\color{red}{better reading experience}}$

Article Directory

In the first chapter, we learned about the hardware that constitutes the computer. To make the computer work normally, the various devices must be connected through lines. Different connection methods have different impacts on the computer's work.

3.1 Basic concept of the bus

3.1.1 Definition of bus

There are two ways of interconnection between the five major components of a computer system:

Decentralized connection: separate connections are used between each component, with the operator as the center;
Bus connection: connects components to a common set of information transmission lines, centered on memory.

Most of the early computers used distributed connections, and their internal connections were very complicated. When I/Oexchanging information between the device and the memory, it had to go through the arithmetic unit, causing the arithmetic unit to stop computing, which seriously affected the CPUwork efficiency of the computer.

From this we lead to the definition of the bus :
The information transmission line connecting each component is the transmission medium shared by each component;
The interconnection mechanism that constitutes a computer system is a public channel for data transmission between multiple system functional components.

The use of bus connections can greatly optimize a series of problems caused by decentralized connections:

insert image description here

CPUA bus is opened between the main memory and the main memory, which is called the memory bus. This set of buses has a high speed and is only used CPUto transfer information between main memory and memory. This not only improves the transmission efficiency, but also reduces the burden on the system bus, and also retains the characteristics that I/Othe device does not pass through when exchanging information with the memory CPU. Most modern computers use various bus structures .

3.1.2 Classification of buses

on-chip bus

On-chip bus: refers to the bus inside the chip. For example, inside the CPU chip, registers and registers, registers and logic units are ALUall connected by on-chip buses.

system bus

System bus: Refers to the information transmission line between the computer CPU, main memory, and major components of the device.I/O

According to the information transmitted by the system bus, it is divided into:

Data bus: transfer data information between functional components. Two-way transmission, the number of bits is related to the machine word length and storage word length.
Address bus: indicates the address of the source data or destination data on the data bus in the main memory unit or the I/Oaddress of the device. For one-way transmission, the number of bits is related to the number of storage units.
Control bus: A transmission line that sends out various control signals. ** For control lines, unidirectional transmission. For the control bus as a whole, bidirectional transmission. **In addition, the control bus also plays a role in monitoring the status of each component. For CPU, the control signal has both output and input.

communication bus

Communication bus: Used for communication between computer systems or between computer systems and other systems.

According to the transmission method, it is divided into:

Serial communication bus: Data is transmitted bit by bit in sequence and time-sharing on a single 1bit-width transmission line, which is suitable for long-distance (thousands of kilometers) data transmission.
Parallel communication bus: Data is transmitted from the source to the destination on multiple parallel bit- 1width transmission lines at the same time, suitable for short-distance (less than 30m) data transmission.

3.2 Bus characteristics and performance indicators

3.2.1 Bus characteristics

The characteristics of the bus can be divided into:

Mechanical characteristics: the physical connection method of the bus (number of roots, plug, socket shape, pin arrangement).
Electrical characteristics: the transmission direction and effective level range of signals on each line.
Functional characteristics: the function of each line (address, data, control).
Time characteristics: It specifies when each bus is valid (timing relationship).

3.2.2 Bus Performance Index

The bus performance indicators are as follows:

Bus width: refers to the number of data buses, use $\text{bit}$ (bit) means that there are as many wires as there are bits.
Bus bandwidth: The data transmission rate of the bus, that is, the number of bits of data transmitted on the bus per unit time, usually measured by the number of bytes of information transmitted per second:
- Unit $\text{MBps}$ (megabytes per second).
- Calculation method: bus operating frequency ( $\text{MHz}$ ） $\times$ bus width ( $\text{B}$ ）。
- Example: The bus operating frequency is $33\text{ MHz}$ with a bus width of $32$ 位（ $\text{ bit}=4\text{ B}$ ), then the bus bandwidth is $33 \times (32 \div 8 ) = 132 \text{ MBps}$ 。
Clock synchronous/asynchronous: A bus whose data on the bus works synchronously with the clock is called a synchronous bus, and a bus that works asynchronously with the clock is called an asynchronous bus.
Bus multiplexing: two signals are time-divisionally transmitted on one signal line, such as address lines and data lines are multiplexed.
Number of signal lines: the sum of the three bus numbers of address bus, data bus and control bus.
Bus control mode: including burst work, automatic configuration, arbitration mode, logic mode, counting mode, etc.
Other indicators: load capacity, power supply voltage, whether the bus width can be expanded, etc.

3.2.3 Bus Standards

Bus standard: It can be regarded as a standard interface for interconnection between the system and each module, and between modules. Its advantages are as follows:

Simplify system design;
Simplify system structure and improve system reliability;
It is convenient for system expansion and update.

In addition, in order to make the same functional components produced by different manufacturers interchangeable, it is necessary to standardize the system bus .

The current popular bus standards are as follows:
ISABus: Introduced by , also known as AT bus, it uses a bus clock IBMindependent of , so you can use a clock with a higher frequency than the bus, which is conducive to improving your performance.CPUCPUCPU
EISABus: Based on ISAthe expanded and open bus standard, ISAit is fully compatible with and separates the bus control right from CPUit . It is an intelligent bus that can support multiple bus masters and burst modes (synthetic block data transfer).
VESABus: VESAThe local bus standard proposed by , also known as VL-BUS(Local BUS) bus. Through the local bus controller, the high-speed I/Odevice is directly connected CPUto the high-speed device to realize high-speed data exchange between the device CPUand the high-speed device.I/O
PCIBus: IntelLaunched by the company, it has the characteristics of high performance, high compatibility, high scalability, multi-master support, plug and play, etc.
ACPBus: IntelIntroduced by the company, it is a local bus dedicated to display cards. It adopts a point-to-point channel method and uses the main memory as a frame buffer to achieve high-speed access.
RS-232CEIABus: A serial communication bus standard recommended by the American Electronics Industries Association .
USBBus: A computer serial interface bus standard jointly developed by seven major companies including Compaq, DEC, IBM, Intel, Microsoft, NECand . It has the characteristics of real plug and play, universal connection, high-speed transmission, and unified standard.Northern Telecom199411

3.3 Bus structure

3.3.1 Single bus structure

insert image description here

The picture shows a single-bus structure. This structure is simple and easy to expand, but all transmissions pass through this group of shared buses , so it is easy to form a bottleneck in the computer system. It also does not allow more than two components to transmit information to the bus at the same time , which will inevitably affect the improvement of system work efficiency.

3.3.2 Multi-bus structure

dual bus structure

insert image description here

I/OThe characteristic of the dual-bus structure is to separate the lower-speed devices from the single bus to form I/Oa structure in which the main memory bus is separated from the bus. The channel in the figure is a processor with special functions, CPUwhich delegates part of the functions to the channel, so that it I/Ohas the function of unified management of the device, so as to complete the data transmission between the external device and the main memory, and the throughput capacity of the system can be quite large . This structure is mostly used in large and medium-sized computer systems.

Three bus structure

insert image description here

In a three-bus architecture, only one bus can be used at any one time. The main memory bus and DMAthe bus cannot access the main memory at the same time, and I/Othe bus can only be used when CPUexecuting instructions. I/OThe following schematic diagram of another three-bus structure:

insert image description here

Extended bus structure

In order to further improve I/Othe performance of the device and make it respond to commands faster, a four-bus structure has emerged.

insert image description here

3.4 Bus Control

3.4.1 Bus Arbitration Control

Many components share the bus. When competing for the right to use the bus, it should be resolved according to the priority of each component .

Bus arbitration control is divided into:

Centralized: Centralize the control logic in one place (such as in the CPU)
Distributed: Distribute the control logic to various components or devices connected to the bus.

Common centralized control priority arbitration methods are as follows:
Chain query : Only a few lines can be used to achieve bus control according to a certain priority, and it is easy to expand equipment, but it is very sensitive to circuit failures, and equipment with low priority may be difficult to obtain requests.
Counter timing query : not as sensitive as the chain query method, but the number of control lines (device addresses) is increased, and the control is more complicated.
Independent request mode : fast electrical response, flexible priority control (changed by program), but the number of control lines is large, and the bus control is more complicated.

3.4.2 Bus communication control

Many components share the bus, and the communication time should time-sharing manner .

That is, the sequence of obtaining the right to use the bus takes up the bus in time-sharing, that is, which part obtains the right to use, it will transmit it at this moment, and the next component will obtain the right to use, and then transmit it at the next moment. In this way, they are transmitted alternately one by one.

Usually, the time to complete a bus operation is called a bus cycle , which is divided into:

Application allocation stage: The master module (or master device) that needs to use the bus submits an application, and the bus arbitration agency decides to grant the bus usage right for the next transmission cycle to a certain applicant.
Addressing stage: The master module that has obtained the right to use sends the address and related commands of the slave module (or slave device) to be accessed this time through the bus, and starts the slave module participating in this transmission.
Data transmission stage: the master module and the slave module exchange data, and the data is sent by the source module and flows into the destination module through the data bus.
End stage: the relevant information of the main module is removed from the system bus, and the right to use the bus is released.

The bus communication control mainly solves how the two parties in the communication know the start and end of the transmission, and how the two parties in the communication coordinate and cooperate. Usually four ways are used: synchronous communication, asynchronous communication, semi-synchronous communication and separated communication.

synchronous communication

The two sides of the communication control the data transmission by a unified time scale, which is called synchronous communication .

The time stamp is usually sent by the bus control part of the CPU and sent to all parts on the bus; it can also be sent by the timing generator of each part, but they must be synchronized by the clock signal sent by the bus control part.

Advantages: The regulations are clear and unified, and the cooperation between modules is simple and consistent.
Disadvantages: The time coordination between the master and slave modules is a mandatory "synchronization", and the specified requirements must be completed within a limited time. And use the same time limit for all slave modules, which will inevitably cause, for parts with different speeds, the common clock must be designed according to the slowest speed parts, which seriously affects the working efficiency of the bus.

In the bus system of synchronous communication, the shorter the bus transmission cycle, the more bits of the data line, which directly affects the data transmission rate of the bus.

asynchronous communication

Asynchronous communication overcomes the shortcomings of synchronous communication, allows the inconsistency of the speed of each module , and gives designers sufficient flexibility and choice.

It does not have a common clock standard, and does not require strict unified operating time of all components, but adopts a response method (also known as a handshake method), that is, when the master module sends a request (Request) signal, it has been waiting for the slave module to return a "response" ( Acknowledge) signal, the communication will start. Of course, this requires adding two response lines (handshaking interaction signal line Handshaking) between the master and slave modules.

Asynchronous communication has the following response methods:

Not interlocked:
- After the master module sends the request signal, it does not need to wait for the response signal from the slave module, but after a period of time, after confirming that the slave module has received the request signal, it cancels its request signal;
- After the slave module receives the request signal, it will send a reply signal when the conditions permit, and after a period of time (the setting of this period is different for different devices) after confirming that the master module has received the reply signal, it will automatically cancel the reply signal.
Half interlock:
- When the master module sends out a request signal, it must cancel its request signal after receiving the reply signal from the slave module, which has an interlocking relationship;
- The slave module sends a response signal after receiving the request signal, but it does not need to wait to know that the request signal of the master module has been cancelled, but automatically cancels its response signal after a period of time, without interlocking relationship.
Fully interlocked:
- The master module sends a request signal, and the request signal must be revoked after the slave module responds;
- When the slave module sends a reply signal, it must cancel its reply signal after knowing that the request signal of the master module has been revoked.

insert image description here

The data transfer rate of asynchronous serial communication is measured by baud rate .

The baud rate refers to the number of bits of binary data transmitted per unit time, and the unit is bpsexpressed in (bit/second), recorded as baud.

semi-synchronous communication

Semi-synchronous communication not only retains the basic characteristics of synchronous communication, but also allows modules of different speeds to work harmoniously like asynchronous communication .

For this reason, a "wait" (WAIT) response signal line is added, and the measure of inserting people's clock (wait) cycle is used to coordinate the cooperation between the two sides of the communication.

Advantages: Its control method is simpler than asynchronous communication, and all modules in the whole system work synchronously under the control of a unified system clock, with high reliability and convenient synchronous structure.
Disadvantages: The system clock frequency cannot be too high, so overall, the system work speed is not very high.

Semi-synchronous communication is suitable for a simple system with a low system working speed but including many devices with different working speeds.

split communication

The above three communication methods start from the address and read and write commands issued by the main module until the end of data transmission. During the entire transmission cycle, the right to use the system bus is completely occupied by the master module that occupies the right to use and the slave module selected by it . Except for the stage of applying for the bus, the rest of the time is mainly spent on the following aspects:

① The master module sends addresses and commands to the slave module through the transmission bus.
② The slave module makes necessary preparations for reading data according to the command.
③ The slave module provides data to the master module via the data bus.

It can be seen from ② that for the system bus, there is no substantial information transmission in the process of reading data from the inside of the module, and the bus is purely idle and waiting .

From this, the idea of separation is proposed :
First, a transfer cycle (or bus cycle) is broken down into two sub-cycles.
In the first subcycle:
- Main module After $A$ $B$ receives.
- Main module $A$ gives up the right to use the bus immediatelyafter releasing the information to the system bus, so that other modules can use it.
In the second subcycle:
- When $Module B$ receives $The command signal sent by module A$ , after internal processing, willWhen the data required by module $A$ $Module B$ applies for the right to use the bus.
- Once approved, $AA$ _ $The data required by module A$ is sent to the bus for module A to receive.
Apparently, the above two transmission sub-cycles have only one-way information flow, and each module becomes the main module.

The characteristics of this communication method are as follows:
Each module must submit an application to occupy the right to use the bus.
After obtaining the right to use the bus, the main module transmits information to the other party within a limited time, and transmits in a synchronous manner without waiting for the reply signal from the other party.
Each module does not occupy the bus during the process of preparing data, so that the bus can accept requests from other modules.
When the bus is occupied, it is doing effective work, or sending commands through it, or transmitting data through it, there is no idle waiting time, and the effective occupation of the bus is fully utilized.

This method is more complicated to control, and is rarely used in ordinary microcomputer systems .