[Computer Composition Principles Notes] System Bus Concept

system bus concept

In order to communicate with each other, each component is connected separately, which is too complicated, so the concept of bus was born

basic concept

Is a set of common information delivery routes that can be time-shared for multiple parts

bus classification

by delivery method

• Serial: 1 bit 1 bit transmission and reception on the bus
• Parallel: Multiple bits are transmitted and received on the bus, requiring multiple data lines

By scope of use

• On-chip bus
  The bus inside the chip
• The system bus
  is an information transmission line between CPU, main memory, and I/O devices, also known as a board-level bus or an inter-board bus
  • The data bus
    transmits data information and is a two-way transmission bus
  • The address bus indicates the address of the source data or target data on the data bus in the main memory unit, which is a single transfer bus
    from the CPU
  • Control bus
    The transmission line that sends out control signals, the single control line is unidirectional , and the overall bus is bidirectional
• Communication bus A
  transmission line used to communicate between computer systems or with other systems
  • serial
  • parallel

bus characteristics

• Mechanical characteristics
  The mechanical connection standard of the bus, such as plug and socket specifications, etc.
• Electrical characteristics Transmission direction and effective level range of signals
  on each transmission line
• Functional characteristics
  Each transmission line in the bus has its own responsible function
• Time characteristics
  Each signal on each bus has a certain effective timing relationship with each other, which can be described by a signal timing diagram

Performance indicators of the bus

• Bus width
  The number of data buses , expressed in bits
• Bus bandwidth
  The data transmission rate of the bus (the number of data bits transmitted per unit time), commonly measured in bytes per second (MBps: Million Byte per second, megabytes per second)
• Synchronously
  • Synchronization: bus data and clock work synchronously
  • async: does not work synchronously
• Bus multiplexing
  A transmission line transmits different signals in time division, and assumes different functional roles at different times
• Number of Signal Lines
  Number of Signal Lines = Address Bus + Data Bus + Control Bus
• Bus control mode
  Burst work, automatic configuration, arbitration mode, logic mode, counting mode, etc.
• Others
  Operating frequency, clock frequency, load capacity, power supply voltage, bus width expansion, etc.

bus standard

• ISA
  • Does not support bus arbitration
  • Data transfer must go through CPU/DMA
  • Clock frequency: 8MHz
  • Maximum transfer rate: 16 MBps
  • Data line: 16 bits
  • Address lines: 24 bits
• EISA
  • Intelligent bus, support burst mode and multi-bus master
  • Clock frequency: 8MHz
  • Maximum transfer rate: 33 MBps
  • Data line: 32 bits
  • Address line: 32 bits
  • Extended DMA access range: 2^32
• VESA(VL-BUS)
  • Local bus, evolved from CPU bus
  • Clock frequency: 33 MHz
  • Maximum transfer rate: 133 MBps
  • Data line: 32 bits, can be expanded to 64 bits through the expansion slot
• PCI
  • GUI rendering
  • high performance
  • good compatibility
  • plug and play
  • Support for multi-master devices
  • Capable of fully parallel operation
  • Supports parity for data and addresses
  • Supports two voltage standards: 5V and 3.3V
  • scalability
  • multiplexing odd
• AGP
  • 3D data processing
• RS-232C
  • Serial communication, data interrupt and binary data exchange interface standard for communication devices
• USB
  • Common Peripheral Serial Link Communication Standard
  • True plug and play
  • Highly unified standard
  • Lightweight connection cables
  • Strong vitality, no patent copyright restrictions

bus structure

single bus structure

All the CPU, main memory and I/O devices are hung on one system bus, and only one pair of components can be connected at the same time

advantage:

• Simple structure, easy to expand

shortcoming:

• Data transfer efficiency is low
• low data throughput

dual bus structure

• Dual-bus structure of the memory center

On the basis of the single bus, a storage bus is opened up, which is responsible for the information transmission between the main memory and the CPU, which not only improves the transmission efficiency but also reduces the burden on the system bus, and also retains the time when I/O devices exchange information with the memory. Features without CPU

• Dual-bus structure of the I/O center

Separation of lower-speed I/O devices reduces pressure on the system bus

• CPU-oriented dual-bus structure

The M bus is also a storage bus. All I/O devices are mounted on the I/O bus through the I/O interface, which is convenient for adding and deleting I/O devices. CPU work efficiency

Three bus structure

The main memory bus is used for information transmission between the CPU and main memory, the I/O bus is used for information transmission between the CPU and each I/O, and the DMA bus is used for information exchange between high-speed peripherals and main memory. In this three-bus structure, the DMA bus and the main memory bus cannot be used to access the main memory at the same time

another form

Four bus structure

Further improvement of I/O performance, high-speed devices and CPU are more closely connected, and low-speed devices are connected through the expansion bus

PCI bus structure

The PCI bus is connected to the system bus through the PCI bridge, so that the CPU bus and the PCI bus are isolated from each other, which has higher flexibility and supports more high-speed devices, while the low-speed devices are mounted on the ISA and EISA buses. When the driving capability of the PCI bus is insufficient, it can be extended to a multi-layer PCI bus structure.