Bus: Each wire carries an electrical pulse signal, representing one bit of binary data. It consists of transmission line + interface + bus controller.
Transmission lines include: information lines (data, address, control bus), power lines, ground lines
The components on the bus need to be connected to the bus through an interface composed of some tri-state gates and buffer registers
characteristic:
Features
According to the nature of the transmitted information: address, data, control
By connecting components: system bus (processor bus), input and output bus (I/O bus)
According to the location of the computer system: on-chip, backplane, inter-board, communication
Physical characteristics (mechanical characteristics): plug, socket, number of pins, fixing method, etc. The number of data transmission bits is divided into serial (one line), parallel (multiple lines)
Electrical characteristics: transfer direction and effective level range
one-way bus
bidirectional bus
Full-duplex: allowing information to be transmitted in two directions at the same time
Half-duplex: only allows information to be transmitted in one direction at the same time
The address bus is an output signal line
The data bus is a bidirectional signal line
The control bus has both output signal lines and input signal lines, but they are all unidirectional
Low level: 0~2.4 High level: 3.6~5
At any time, there can only be one direction of information flow, ensuring the uniqueness of information
Classification:
On-chip bus: The internal bus of the microprocessor, which is used for the interconnection and information transmission between the ALU and various registers in the microprocessor. Divided into single, dual, triple bus
System Bus: The information transmission line between computer components. Transfer data, address, and control information, respectively corresponding to three buses. Also known as internal bus, microcomputer bus, backplane, board level, and inter-board bus.
Data Bus
Address bus: issued by the CPU, the size of the accessible storage space is 2^n
Control bus:
External bus (communication bus/device bus): connects communication between two systems. It is not inherent in the microcomputer system itself, only in the microcomputer application system.
Classic structure: Microcomputer consists of microprocessor, main memory, I/O interface and system bus, including BIOS
Features: Mutual exclusion of sending and sharing of acceptance. The bus controller manages the bus, and the bus component controlled by the bus becomes the master component/master device of the bus, and the accessed slave component/device.
Bus arbitration: centralized bus arbitration (serial link/chain query, timing query/counter timing query, independent request), distributed bus arbitration
Chain query: physical queuing circuit implementation, sensitive to circuits
Counter timing: After the arbiter receives the request, the count value is sent to each device through a set of address lines when the BS line is 0. Each device interface has a device address discrimination circuit. The count value on the address line is consistent with the address of the bus device. The BS line is 1, the right to use the bus is obtained, and the counting query is terminated. The order of priority is fixed, and the one with the smaller address has the higher priority. Every time the stop point starts, the priority of each device is equal
independent request
Bus communication: the source component sends out data, and the destination component receives data.
Synchronous communication:
Asynchronous communication:
Unilateral control: source component or destination component control
Bilateral control: joint control of both
Two response lines are added between the master and slave modules:
Semi-synchronous communication: macro-synchronous, local asynchronous
Each operation only occurs at a fixed time determined by the clock
The time interval of the control signal can be lengthened and must be an integer multiple of the clock cycle
Split Communication: Synchronous Communication
Subcycle 1: The main module applies for occupying the bus, and gives up the right to use the bus after use
Subcycle 2: The slave module applies for occupying the bus and transmits information
bus performance
Bus width: directly affects the transmission rate (throughput)
Working clock frequency: provided by the clock signal line in the control bus
Standard transfer rate (bandwidth): the maximum number of bytes MB/S that can be transferred per second. Bus bandwidth = bus bit width x bus operating frequency/8
Load capacity: the maximum number of parts that can be connected
Bus multiplexing: functional address line and data line multiplexing
Number of signal lines: the sum of the three bus numbers of address, data, and control
Timing protocol (handshake mechanism)
Bus standard:
ISA: The working frequency is about 8MHz, the data line is 16 bits, the address line is 24 bits, and the expansion card can be connected
EISA: 32 data lines, 32 address lines, clock 8MHZ, compatible with ISA, transfer rate 33MB/S
VL-BUS: local bus application. The data bus width is 32, the address width is 32, and the maximum space for bus addressing is 4GB
PCI Peripheral Device Interconnect Bus:
Multilayer PCI
AGP
PCI-Express
I/O standard distance
USB
IEEE1394
Baud rate = 1/binary bit duration = number of binary signals transmitted per unit time
Bit rate = baud rate × binary number corresponding to a single modulation state
