1, wherein the machine instructions
Command is a command to perform an action computer.
Instruction is a machine instruction in a computer set . It determines a computer's hardware key performance and basic functions , is a hardware and software interface , is the machine hardware design basis and software design basis, directly affects the performance of the computer system.
A machine instruction should include the following information:
● Opcode : This instruction specifies the type of operation to be completed.
● source operand REFERENCE : indicates where to obtain a source operand.
● result operand reference : specify where to store the results of operations.
● next instruction references : Indicates the next instruction.
Operands can be stored positions:
● main memory or virtual memory : providing a main memory or a instruction virtual memory address.
● the CPU registers : the instruction register number provided.
● the I / O device : providing the peripheral address instruction.
Machine instructions in a computer with a binary bit string representation; for easy reading and memory, can mnemonic indicates:
bit string representation : 10010110
mnemonic : ADD R1, R2
above is equivalent to two instructions: (Rl) + (R2) -> R1
Design instruction needs to consider the following information:
● Operating list : command system shall provide the number, type and complexity of the operation.
● Data Type : instruction which needs to operate on several data.
● instruction format : command length, fields, Field Meaning;
● registers : an instruction register can be accessed and their functions;
● addressing : How to form the effective address of the operand, operand acquisition.
System performance requirements of the Directive:
● Completeness : instruction rich, full-featured, easy to use.
● effectiveness : programs written to run efficiently, small footprint, fast execution speed.
● regularity : symmetry, uniform Qi, consistency.
● Compatibility : Series machines upward compatible, non-compatible software compatibility.
Two direction instruction set:
● a complex instruction set computer CISC : instruction set large, long design period, implementation complexity, low hardware utilization.
● reduced instruction set computer RISC : Reduced Instruction system, single-cycle instruction, the instruction format is simple, simple addressing.
2, the data type and the type of operation
Data is usually divided into the following four categories:
● Address : unsigned integer, to determine the position of the operand in main memory by a certain operation
● numerical data : fixed-point integer, decimal point (twos complement); float (IEEE-754) ; packed decimal (BCD code)
● character data : strings of text or data, ASCII code
● logical data : a plurality of binary bits
Type of operation are the following:
● data transmission : between registers comprises, between the memory cells, data transfer between registers and memory unit
● Data processing : for data arithmetic operations, logic operations, shift operations, comparison calculation
● program control : a control sequence program execution, the program makes a test, analysis, judgment; there are branch instructions, the subroutine call instruction and a return instruction
● O : read data from the peripheral register into CPU registers; or the data output from the CPU to the peripheral register and register
3, the instruction format
Instruction basic format : opcode address code +; opcode specifies what operation is completed, the address code indicating that the data came from, where the result to go, where the next instruction fetch.
Instruction format is divided into:
● opcode structure
Operation code field of the instruction determine the number of bits allowed in many computer. The opcode field bits is fixed or can be divided into:
- Fixed length opcode :
instruction opcode all instructions fixed length , fixed position , in a focus field of the instruction.
Digit operation code reflects the machine operation type and the permitted number of extra instructions .
Features: simplify hardware design, reduced instruction decode time, the longer widely used in computers and small and medium-sized word length supercomputers. - Variable length opcode :
instruction opcode field of bits is not fixed , and is dispersed in the instruction word stored in different locations on.
The method of extended operation codes : using a fixed-length field showing a basic operation code, or instruction section need not only address code, the opcode extension to address code field.
For example: Suppose a 16-bit word length computer instructions, wherein four substantially opcode field, three additional 4-bit long code field of the address bits A1, A2, A3. Please use the "extended opcode art" design instructions 61, wherein the three-address instruction 15, two address instruction 15, one address instruction 15, instruction 16 address zero.
For three-address instruction : the first 4-bit opcode preferably 0000 to 1110, the address code 12, a total of 15.
Of the two address instruction : the first 4 bits of the operation code 1111, after 4 preferably 0000 to 1110, after eight address code of 15.
For single-address instruction : first 8-bit opcode is 11111111, then 4 preferably 0000 to 1110, after the address code of 4 bits, a total of 15.
To zero address instruction : ~ 1111111111111111 1111111111110000 preferably, of 16. A total of 61 or more instructions.
Whatever expansion mode, when the design variable length instruction opcode, try to make a high frequency of operation code instructions take short, often used to shorten the instruction decoding time .
● Address code structure
Address code for indicating a source operand address , the result address and the next instruction address . Address may be a main memory address , register address and I / O device addresses .
In the operation of instruction length and the code length is constant, it will affect how many address code addressing range . Depending on how much the number of address code can be divided into:
- Four-address instruction : specifies two operands, the result address and the address of the next instruction. Intuitive but the address of the smaller addressing range .
- Three-address instruction : the address of the instruction subsequent program counter PC provided. The remaining three can be increased addressing range addresses.
- Two address instruction : The source operand address A1 or A2 as the address for storing the result. Addressing further expand the range of addresses.
- Single-address instruction : an operand in a hidden manner in the accumulator ACC given in. Expand the addressable range of addresses.
- Instruction address zero : only the operation code is not the address, the address code indicates that no, or one / two implicit instruction address.
The source operand and a destination operand storage position , two address instruction may be divided into three categories:
● memory - the memory type instruction (SS type)
● Register - register type instruction (RR type)
● Register - memory type instructions (RS type)
RR type instruction execution speed of the fastest.
● instruction word length
The operation code and address code merged into the instruction . Instruction word length refers to the instruction contained in a binary code bits, depending on the operation code length and the number of address code .
The instruction word length can be divided into:
● fixed-length instruction word : instruction length is equal to all of the command system, the length of the longest line to the instruction set.
● Variable length instruction word : different instruction length instruction varies, with different functions, can be as short short, long or as long as required.
4, addressing
Addressing way : for each storage device mode number. There are:
● Word Addressing : In memory word units numbering
● byte addressing : in byte units numbered
addressing : find ways to the next instruction and operand addresses. It can be divided into:
● instruction addressing
- Sequential addressing : program execution sequence of instructions when addressing mode. A program counter to increment operator records the address of the next instruction in memory.
- Jump address : program branch executing instructions when addressing mode. Program counter contents are not changed by the self-energizing sequence, while the branch instruction is given.
● data addressing
Address form : the instruction address code field of the address, with A represents.
Effective Address : true address of the operand with EA represents.
Data addressing is based on the address code field operand in the memory device form the real address mode.
Data addressing mode:
- Addressing now : A form of the address is given in the operand itself.
Advantages: no need to access memory, execution speed; disadvantages: the operand address field size is limited by length restrictions. - Direct Addressing : form effective address given by the address, i.e. EA = A .
Features: Just once to access memory, faster execution; median A decision addressing range. - Indirect addressing : Indirect effective address given by the address form, i.e. EA = (A) .
Features: the need to repeatedly access memory, slower execution speed; expand the addressing range. - Register Addressing : operands in register, the effective address is the register number, i.e. EA = Ri of (Ri of A =).
Features: No access memory, execution speed; limited number of registers, instruction word length can be shortened. - Register indirect addressing : operand in memory address of the operand in the register, i.e. EA = (Ri of) .
Features: instruction execution stage need access memory, to facilitate the preparation of circular program. - Implied addressing : the operand address implicit in the register or accumulator in.
Features: at least one instruction word address code field, instruction word length can be shortened. - Offset addressing : direct addressing and indirect addressing binding, the address of the operand required by calculation. Offset addressing it can be divided into:
● Relative Addressing : effective address EA = (the PC) + A .
● based addressing : the effective address EA = base address register A + . Expansion instruction addressing range. Extremely useful in multi-channel programming and floating programming.
● indexed addressing : effective address EA = index register A + . It facilitates the handling of an array of issues. - Stack Addressing : no address code, a valid address is stored in the stack .
