Principles of Computer Organization (Third Edition) Tang Shuofei - Chapter 3 System Bus - Exercises after class

third chapter

3.1 What is a bus? What are the characteristics of bus transmission? In order to reduce the load on the bus, what characteristics should the components on the bus have?

Answer:
①busIt is an information transmission line connecting multiple components and a transmission medium shared by components.
② Bus transmissionfeatures: At a certain moment, only one component is allowed to send information to the bus, while multiple components can receive the same information from the bus at the same time.
③ In order to reduce the load on the bus, various I/O devices must passI/O connectorConnected to the bus, but also through theTri-state gateHanging on the bus, set to a high-impedance state when there is no data exchange.

3.2 How are buses classified? What is a system bus? The system bus is divided into several categories. What are their functions? Is it unidirectional or bidirectional?

Answer:
according toconnecting partsdifferent, the bus can be divided intoOn-chip bus, system bus and communication bus。
system bus: It is an information transmission line connecting CPU, main memory, and I/O components.
system bus according totransmit informationdifferent and divided intoAddress lines, data lines and control lines。
address lineIt is unidirectional, the more roots, the larger the addressing space, that is, the more storage units the CPU can access;
data lineIt is bidirectional, and its root number is the same as the storage word length, which is an integer multiple of the machine word length.
control busis bidirectional.

3.3 How many types of bus structures are commonly used? What impact do different bus structures have on computer performance? Give an example.

Answer:
The commonly used bus structure isSingle bus structure, double bus structure, three bus structure, four bus structure.
(1) Single bus structure: hang the CPU, main memory, and I/O devices on a set of buses, allowing direct exchange of information between I/O or between I/O and main memory. Because all transmissions pass through this group of shared buses, it is very easy to form a bottleneck in the computer system, and two or more components are not allowed to transmit information to the bus at the same time, which will inevitably affect the improvement of system work efficiency. The structure diagram is shown in Figure 3.2 of the textbook. ISA, EISA bus is a single bus structure.

(2) Dual-bus structure: The feature of the dual-bus structure is to separate the lower-speed devices from the bus to form a structure in which the main memory bus and the I/O bus are separated, see Figure 3.7 in the textbook. The channel in the figure is a processor with special functions. The CPU delegates some functions to the channel, so that it has the function of unified management of I/O devices, and the throughput capacity of the system can be quite large. If you classify I/Os with different rates, and then connect them to different channels, it will become a bus structure.
(3) Three-bus structure: Figure 3.8: The main memory bus is used for the transmission between the CPU and the main memory; the I/O bus is used for transferring information between the CPU and various I/Os, and the DMA bus is used for high-speed peripherals (disk, tapes, etc.) to exchange information directly with main memory. Figure 3.9: What is a local bus between the processor and the cache? Cache can transfer information to the main memory through the system bus, and there is no need to pass through the CPU between I/O and the main memory. There is also an expansion bus that can support quite a few I/O devices.


(4) Four-bus structure (see Figure 3.10) On the basis of three buses, a high-speed bus that is confidentially connected to the computer system is added. For high-speed devices, their own work can rarely rely on the processor, and at the same time they It is closer to the processor than the devices on the expansion bus.

3.4 Why do you need to set up bus arbitration control? There are several common centralized bus controls, what are their characteristics, which method has the fastest response time, and which method is most sensitive to circuit failures?

Answer:
(1) If multiple master devices want to use the bus at the same time, the arbitration and arbitration logic of the bus controller will determine which master device can use the bus according to a certain priority order, and only the master device that has obtained the right to use the bus to start transferring data. (2) There are three
common centralized bus controls①
chain query: It is characterized in that only a few wires can realize bus control according to a certain priority order, and it is easy to expand equipment, but it is very sensitive to circuit failure.
②Counter Timing Query: Its characteristic is that the counting can start from "0", at this time the priority of the device is fixed, and the counting can also start from the end point, which is a cycle mode, at this time, the priority of the device using the bus is equal, and the initial counter Values ​​can also be set by the program, so the priority can be changed. In addition, it is not as sensitive to circuit faults as the chain query method, but the number of main control lines is increased, and the control is more complicated.
③independent request method: Its characteristics are: fast response, flexible priority control (change through program), but the number of control lines is large, and the bus control is more complicated.
④ The independent request mode has the fastest response time, and the chain query is the most sensitive to circuit failure.

3.5 Explain concepts: bus width, bus bandwidth, bus multiplexing, bus master (or master module), bus slave (or slave module), bus transmission cycle, bus communication control.

answer:
bus width: Usually refers to the number of data buses;
bus bandwidth: The data transmission rate of the bus refers to the number of bits of data transmitted on the bus per unit time;
bus multiplexing: It means that the same signal line can transmit different signals in time division.
Master of the bus (master module): Refers to the device (module) that has the right to control the bus during a bus transmission;
Slave device of the bus (slave module): Refers to the device (module) that cooperates with the master device to complete data transmission during a bus transmission, and it can only passively accept the commands sent by the master device;
Bus transfer cycle: refers to the time required for the bus to complete a complete and reliable transmission;
Bus communication control: Refers to the time coordination mode of both parties during the bus transmission process.

3.6 Try to compare synchronous communication and asynchronous communication.

answer:
synchronous communication: Refers to the communication controlled by a unified clock. The control method is simple and the flexibility is poor. When the working speed of each component in the system varies greatly, the working efficiency of the bus will drop significantly. It is suitable for occasions where there is little difference in speed.
asynchronous communication: Refers to the communication without unified clock control, and the components are connected by the response method. The control method is more complicated than synchronous, and the flexibility is high. When the working speed of each component in the system differs greatly, it is beneficial to improve the efficiency of the bus.

3.7 Draw a picture to illustrate the interlocking relationships between requests and responses in asynchronous communication.

Answer:
The response methods of asynchronous communication can be divided into three types: no interlock, semi-interlock and full interlock, as shown in the figure below.

3.8 Why is it said that semi-synchronous communication retains the characteristics of synchronous communication and asynchronous communication at the same time?

Answer:
Semi-synchronous communication retains bothsynchronous communicationThe basic characteristics of the system, such as the sending time of all addresses, commands, and data signals, are strictly based on a certain leading edge of the system clock, and the receiver uses the time of the trailing edge of the system clock to judge and identify; at the same time, it is likeasynchronous communicationThat way, modules of different speeds are allowed to work harmoniously. To this end, a "wait" (WAIT) response signal line is added. useInsert clock (wait) cyclesMeasures to coordinate the cooperation between the two parties in communication.semi-synchronous communicationIt is suitable for a simple system composed of many types of equipment with low working speed but with a large difference in working speed. The semi-synchronous communication control method is simpler than asynchronous communication, and each module in the whole system is controlled by a unified system clock. Synchronous work, high reliability, more convenient synchronization structure. ThatshortcomingThe reason is that the system clock frequency cannot be too high, so overall, the working speed of the system is not very high.
Therefore, semi-synchronous communication can not only be controlled by a unified clock like synchronous communication, but also allow inconsistent transmission time like asynchronous communication, so the work efficiency is between the two.

3.9 What are the characteristics of separate communication? What system is it mainly used for?

Answer:
The characteristics of separate communication are:
(1) Each module must apply for the right to use the bus;
(2) After obtaining the right to use the bus, the main module transmits information to the other party within a predetermined time, and transmits in a synchronous manner , no longer waiting for the response signal from the other party;
(3) Each module does not occupy the bus during the process of preparing data, so that the bus can accept requests from other modules; (
4) When the bus is occupied, it is doing effective work, or through it Sending commands, or transmitting data through it, there is no idle waiting time, and the occupation of the bus is fully utilized, thereby realizing the cross-overlapped parallel transmission of information between multiple master and slave modules on the bus.
Separate communication is mainly used forlarge computer system。

3.10 What is a bus standard? Why should a bus standard be set? What are the current popular bus standards? What is plug and play, and which buses have this feature?

Answer:
　　the so-calledbus standard, can be regarded as a standard interface for interconnection between the system and each module, and between modules. This interface is transparent to the modules at both ends of the interface, that is, either side of the interface only needs to complete the functional requirements of its own interface according to the requirements of the bus standard, and does not need to know the connection requirements of the other interface and the bus. Therefore, the interface designed according to the bus standard can be regarded as a general interface.
　　The use of bus standards can provide support for the design of software and hardware for computer interfacesconvenient. For hardware design, the interface chip design of each module is relatively independent; for software design, it is more conducive to the modular design of interface software.
　　Currently popular bus standards are as follows:
　　(1) ISA bus:
　　(2) EISA bus;
　　(3) VESA (VL-BUS) bus:
　　(4) PCI bus:
　　(5) AGP bus;
　　(6) RS- 232C bus;
　　(7) USB bus.
　　plug and play(Plug and Play): That is, any expansion card can work as long as it is inserted into the system. PCI devices are equipped with registers for storing device specific information, which can be used by BIOS (basic input and output system) and operating system layer software to automatically configure PCI bus components and plug-ins, making the system easy to use without complex manual configuration. PCI, USB and other buses have the characteristics of plug and play.

3.11 Draw a logic diagram of a bus with bidirectional transfer function.

Answer:
By configuring three-state gates at both ends of the bus, the bus can have bidirectional transmission function, as shown in the figure below:

3.12 Assuming that there are 4 registers A, B, C, and D connected to the data bus, it is required to select a suitable 74 series chip to complete the following logic design:

(1) Design a circuit to realize the transfer between D→A, D→B and D→C registers at the same time.
(2) Design a circuit to realize the following operations.
$$\begin{gathered} T_{0}completeD\to bus. \\ {T}_{1}Time\; to\; complete\; the\; bus\to A。 \\ {T}_{2}CompleteA\; all\; the\; time\to bus. \\ {T}_{3}Time\; to\; complete\; the\; bus\to B.\_ \end{gathered}$$
Answer:
(1) T opens the three-state gate to send the contents of the D register to the bus bus, and the cp pulse simultaneously inputs the data on the bus into the A, B, and C registers. The time relationship between T and cp is shown in the figure below.

(2) Tri-state gate 1 is controlled by T0+T1 to ensure D→bus at T0, and bus→receiving gate 1→A at T1. Tri-state gate 2 is controlled by T2+T3 to ensure that A→bus at time T2, and bus→receiving gate 2→B at time T3. The waveforms of T0, T1, T2, and T3 are shown in the figure below:

3.13 What is the data transfer rate of the bus, and what factors is it related to?

Answer:
The data transmission rate of the bus is the bus bandwidth, which refers to the number of bits of data transmitted on the bus per unit time, usually measured by the number of bytes of information transmitted per second.
It is related to bus width and bus frequency. The wider the bus width, the faster the frequency and the higher the data transmission rate.

3.14 Let the clock frequency of the bus be 8MHz, and one bus cycle is equal to one clock cycle. If 16 bits of data are transmitted in parallel in one bus cycle, what is the bandwidth of the bus?

Answer:
Because: f=8MHz, T=1/f=1/8M seconds, one bus cycle is one clock cycle
So: bus bandwidth=16/(1/8M) = 128Mbps

3.15 In a 32-bit bus system, the clock frequency of the bus is 66 MHz, assuming that the shortest transmission cycle of the bus is 4 clock cycles, try to calculate the maximum data transmission rate of the bus. What steps can be taken to increase the data transfer rate?

Answer:
The bus transmission cycle = 4*1/66M seconds
The maximum data transmission rate of the bus = 32/(4/66M) = 528Mbps
If you want to increase the data transmission rate, you can increase the bus clock frequency, increase the bus width or reduce the bus transmission cycle The number of clock cycles involved.

3.16 In the asynchronous serial transmission system, the character format is: 1 start bit, 8 data bits, 1 check bit, 2 stop bits. If it is required to transmit 120 characters per second, find out the baud rate and bit rate of transmission.

Answer:
A frame contains: 1+8+1+2=12 bits
, so the baud rate: (1+8+1+2)*120=1440bps
bit rate: 8 *120=960bps