xilinx FPGA DDR3 IP core (VHDL&VIVADO) (user interface)

This article only talks about the user interface and not the AIX4 interface

There are many introductions about ddr3 on the Internet. To describe it in a more popular language, it is the large-capacity storage unit in the fpga development board. Because it is usually possible to use rom or fifo directly, but resources are limited, you can use ddr to replace. In fact, ddr3 is very similar to ram, that is, it has read and write addresses, and then can read and write corresponding data.

Then the biggest difference is that the ip core of ddr3 is divided into the physical layer and the user side. We only need to apply the pins on the user side.

The following figure is a schematic diagram of the user interface:

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Then build the ip core:

You can see whether the device model and hardware language are what you want for your project. If not, you can cancel and go back to the setting to reset (it doesn’t matter if it’s just emulation, and you need to choose the right one if it’s board verification)

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Only verilog can choose the AXI4 interface, and others can be selected as shown in the figure below:

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The target device defaults to the selected device:

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Choose DDR3:

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The following is an important link, about the clock setting of DDR3

PS: Let me talk about the model of the ddr3 chip first, for example: MT41J128M16XX-125, where 16 refers to the bit width, you can calculate its capacity (that is, the maximum amount of data that can be written without reading) 128M*16bit=1024MByte; 125 refers to tck=1.25ns, that is, the maximum IO clock frequency is 1/1.25ns=800MHZ (the frequency of DDR3); then the transmission rate is 2*800=1600Mbit/s (because it is a double clock edge transmission); then the bandwidth (16 Data line transmission rate) 1600Mbit/s*16=25600Mbit/s=3.125GBbit/s

In ddr3, there are two clocks, the reference clock (200MHZ) and the system clock, so when the system clock is 200MHZ, the same clock can be used. (That is to say, if you want to use ddr3, you need to provide these two clocks. Generally, the FPGA development board multiplies the clock pll of the crystal oscillator and then gives it to ddr3, so we can use 200MHZ, and only one pll multiplier clock is needed. That’s it. In addition, when configuring the ip core, you can choose no buffer for the source of the system clock, because the pll frequency multiplier from fpga is not a separate clock source input, then you can choose the system clock as the reference clock, here The system clock refers to the system clock of the ddr3 ip core)

Three clocks will be generated in the mig IP core of ddr3, the first one is clk_period:

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In the end, keep going to next

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The chip selection signal (Controller Chip Select Pin) is set to Enable, that is, using this pin, the actual development board

The CS signal of DDR3 is connected to the FPGA pin, so this pin needs to be used here. If the hardware is DDR3

If the pin is not connected to the FPGA, it can be set to Disable here.

Reference Clock (Reference Clock): This clock needs a clock frequency of 200MHz, because the previous configuration will

The system clock is set to 200MHz, so you can choose Use System Clock, so that the two input

The clocks are combined to a common 200MH input. If the previous system clock setting is not 200MHz, configure here

If there is no “Use System Clock” option, the clock can only be input by the pin port or the internal product of FPGA.

Generate this 200MHz clock.

sys_rst is the system reset input signal of IP, low level reset

Experiment 2: Because the bit width of ddr3 is relatively large, it is necessary to add a fifo at both ends to convert the clock and bit width

Then the data is first written into fifo0 (as long as fifo0 is not full, it can be written all the time), and then the data of fifo0 is read into ddr3 (change fifo to use FWFT mode, that is, rd_en and fifo_dout are valid at the same time, and the writing of rd_en and ddr3 is enabled signal connection), then read and write ddr3 data to fifo1 (keep writing until fifo1 is not full, connect ddr3 read data and read data valid signal to fifo1 write data and write enable respectively), Later, according to the timing of reading data, you can read data when fifo1 is not free (here, as long as fifo1 is not free, read all the time)

The following is the timing diagram captured by ILA:

It can be seen that after ddr3 is initialized successfully, incremental data (1——50) is written to fifo0

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When app_en, app_rdy, and app_wdf_rdy are all valid, and fifo0's empty=0, enable fifo0's rd_en

and app_wdf_wren of ddr can read the data of fifo0 to app_wdf_data, as shown in the figure below, when the address is 0, 0001...0008 is written, because in addition to the address, the others use combinational logic, so follow the clock is not aligned

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It can be seen that the first number read by ddr3 is the data written into address 0

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It can be seen that the first data read by fifo1 is 1 (this is because fifo1 uses the standard mode, then the read data will be delayed by one clock cycle than the read enable)

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xilinx FPGA DDR3 IP core (VHDL&VIVADO) (user interface)

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