Article directory
foreword
In my previous projects, they were all relatively general design projects, and no IP core was used, so the code has good portability; today I will talk about the first phase of DDS based on the chip of Xilinx manufacturer. For design and verification, the EDA tool I use here is Vivado 2018.3, which integrates the IP core of DDS, and we can call it directly.
Xilinx is the main manufacturer of FPGA. Even in the current FPGA field, it has a great say. At present, there are two main FPGA chips on the market, Xilinx and Altera. The application is even more proficient. We all know that the advantage of FPGA is based on its programmability, which makes its development cycle short, but in order to improve the cycle of FPGA development, each company provides some IP cores with general functions, including hard IP cores solidified in the chip. And the soft IP core that can be programmed and called, and the instantiation and calling functions of IP and are provided in the development tool. Next, I will call the DDS IP core in Vivado for design.
1. Overview of DDS IP core
The above figure is the scheme diagram of the DDS IP core. From the figure, we can see that the DDS IP core is mainly composed of 5 parts. The core of the DDS IP core is the phase accumulator and the LUT lookup table. They can be used independently or together with a used with the optional phase generator. The phase accumulator realizes the generation of the address of the look-up table, and the LUT look-up table is used to store the output waveform. There is also a Taylor series correction module and a jitter generator to improve SFDR. The two sides are the AXI4 interface, which is an interface module based on the AXI4 bus protocol, which is used to realize phase accumulation word configuration, multi-channel configuration, phase accumulator output and sin/cos waveform output.
2. DDS IP core configuration
1. First create a project file, then click IP Catalog, search for DDS directly in the search box, and create a DDS IP core.
2. Then double-click DDS Compiler to enter the DDS IP core configuration interface.
The DDS IP core can be configured into three modes, namely phase accumulator and SIN/COS LUT mode, only phase generator mode, and only SIN/COS LUT mode; here we choose the first phase accumulator and SIN/COS LUT mode .
Input clock: according to the system clock, I choose 100MHz here
Number of channels: I choose single channel here
There are two types of parameter selection: system parameter (System Parameter) and hardware parameter (Hardware Parameter). When selecting system parameters, it is necessary to calculate SFDR and FR (frequency control word) according to the frequency bit width; when selecting hardware parameters, directly define the output The phase width and frequency width are enough. I choose the hardware parameters here. The phase width is 32 bits, and the frequency bit width is 8 bits.
According to the Xilinx official manual, the relationship between phase width (phase width), Frequency Resolution (frequency resolution), channels (number of channels), output width (output waveform bit width), and SFDR is:
Regarding the different bit widths of the output width, the output data format is as follows:
3. Enter the configuration interface on the second page to configure the frequency control word, phase control word and output waveform.
Since different frequency signals need to be continuously output in this experiment to achieve the purpose of a frequency sweep, both the frequency controllable word and the phase control word are set to programmable mode, and the output waveform is a sine-cosine waveform. If you want to output a waveform with a fixed frequency, you can choose the lock mode. This can be changed according to experimental requirements.
4. The third and fourth pages are not required for this experiment, just keep the default. On the fourth page, since the frequency control word is programmable, it will be changed in the code, so there is no need to do any processing here.
5. The fifth page is the configuration overview interface, where you can see the information you have configured, so that you can check whether there is any problem with the configuration.
6. Finally, click OK to generate the DDS IP core, and then instantiate the DDS IP core into the project we designed, and then it can be used directly.
3. Call the DDS IP core
Call the DDS IP core to realize the frequency sweep signal. The frequency sweep range I designed here is 1KHz--10KHz. By controlling the frequency control word to change the frequency of the output waveform, let it change directly from 1KHz to 10KHz, and let it change from 10KHz To 1KHz, it is displayed in the form of a triangular wave in the frequency domain.
1. Top-level module
`timescale 1ns / 1ps
//
//
// Create Date: 2023/03/16 09:54:38
// Design Name: 卡夫卡与海
// Module Name: DDS_top
// Project Name: DDS顶层模块
//
//
//
module DDS_top(
input sys_clk ,//系统时钟 100MHz
input sys_rst_n ,//系统复位
output m_data_tvalid ,//数据有效标志
output [7:0] m_data_sin ,//sin波形
output [7:0] m_data_cos //cos波形
);
//中间信号定义
wire s_phase_tvalid ;//相位有效标志
wire [31:0] s_phase_tdata ;//相位控制字
wire s_config_tvalid ;//频率有效标志
wire [31:0] s_config_tdata ;//频率控制字
wire m_phase_tvalid ;//输出相位有效标志
wire [31:0] m_phase_tdata ;//输出相位
wire [15:0] m_data_tdata ;//输出为16位，高8位是sin波形，低8位是cos波形
//assign m_data_sin = m_data_tdata[15:8];
//assign m_data_cos = m_data_tdata[7:0];
assign m_data_sin = {~m_data_tdata[15],m_data_tdata[14:8]};//将输出转为有符号数据输出 sin
assign m_data_cos = {~m_data_tdata[7],m_data_tdata[6:0]} ;//将输出转为有符号数据输出 cos
//模块例化
//DDS_IP模块
dds_compiler_0 u_dds_0 (
.aclk (sys_clk ),// input wire aclk
.s_axis_phase_tvalid (s_phase_tvalid ),// input wire s_axis_phase_tvalid
.s_axis_phase_tdata (s_phase_tdata ),// input wire [31 : 0] s_axis_phase_tdata
.s_axis_config_tvalid (s_config_tvalid),// input wire s_axis_config_tvalid
.s_axis_config_tdata (s_config_tdata ),// input wire [31 : 0] s_axis_config_tdata
.m_axis_data_tvalid (m_data_tvalid ),// output wire m_axis_data_tvalid
.m_axis_data_tdata (m_data_tdata ),// output wire [15 : 0] m_axis_data_tdata
.m_axis_phase_tvalid (m_phase_tvalid ),// output wire m_axis_phase_tvalid
.m_axis_phase_tdata (m_phase_tdata ) // output wire [31 : 0] m_axis_phase_tdata
);
//控制模块
dds_control u_dds_control(
.clk (sys_clk ),//时钟
.rst_n (sys_rst_n ),//复位
.phase_valid (s_phase_tvalid ),//相位有效标志
.phase_data (s_phase_tdata ),//相位控制字
.config_valid (s_config_tvalid),//频率有效标志
.config_data (s_config_tdata ) //频率控制字
);
endmodule2. DDS IP core control module: control the change of frequency control word
`timescale 1ns / 1ps
//
//
// Create Date: 2023/03/16 10:26:29
// Design Name: 卡夫卡与海
// Module Name: dds_control
// Project Name: DDS控制模块
//
//
//
module dds_control(
input clk ,//时钟
input rst_n ,//复位
output phase_valid ,//相位有效标志
output [31:0] phase_data ,//相位控制字
output config_valid ,//频率有效标志
output [31:0] config_data //频率控制字
);
//参数定义
parameter F_word_1KHz = 32'hA7C5 ;//1KHz频率控制字 M = 1_000*2^32/100_000_000
parameter F_word_10KHz = 32'h68DB8 ;//10KHz频率控制字 M = 10_000*2^32/100_000_000
parameter F_word_change = 32'h1 ;//1KHz-10KHz变化精度
//信号定义
reg [31:0] config_data_reg ;//频率控制字寄存器
reg max_flag ;//当频率控制字最大时，拉高
//max_flag
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
max_flag <= 1'b0;
end
else if(config_data_reg >= F_word_10KHz)begin
max_flag <= 1'b1;
end
else if(config_data_reg == F_word_1KHz)begin
max_flag <= 1'b0;
end
end
//控制频率控制字均匀变化
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
config_data_reg <= F_word_1KHz;
end
else if(max_flag == 1'b1)begin
config_data_reg <= config_data_reg - F_word_change;
end
else begin
config_data_reg <= config_data_reg + F_word_change;
end
end
//输出
assign phase_valid = 1'b1;
assign phase_data = 32'h0;//设置相位控制字为0
assign config_valid = 1'b1;
assign config_data = config_data_reg;
endmodule3. Simulation module
`timescale 1ns / 1ps
//
//
// Create Date: 2023/03/16 14:04:09
// Design Name: 卡夫卡与海
// Module Name: DDS_top_tb
//
//
//
module DDS_top_tb();
reg sys_clk ;
reg sys_rst_n ;
wire m_data_tvalid ;
wire [7:0] m_data_sin ;
wire [7:0] m_data_cos ;
//模块例化
DDS_top u_DDS_top(
.sys_clk (sys_clk ),//系统时钟 100MHz
.sys_rst_n (sys_rst_n ),//系统复位
.m_data_tvalid (m_data_tvalid),//数据有效标志
.m_data_sin (m_data_sin ),//sin波形
.m_data_cos (m_data_cos ) //cos波形
);
//产生激励
initial begin
sys_clk = 1'b0;
sys_rst_n = 1'b0;
#20;
sys_rst_n = 1'b1;
#20000000;
$stop;
end
always #5 sys_clk = ~sys_clk;
endmodule4. The simulation waveform is as follows:
Through the simulation waveform, it can be seen that a continuously changing sine wave and cosine wave are generated, and the waveform changes periodically from slow to fast and then from fast to slow, which meets the design requirements.
Summarize
The configuration of the DDS IP core is relatively simple. When using the packaged IP core, whether it is Xilinx or Altera, it is still very important to read the official manual. It is only in pure English, but it can improve our English reading ability. Well! When you read many IP core manuals, you will find that the layout of those manuals is basically the same, so it is not so strenuous to read.