In communication theory, the effectiveness of a communication system is measured by bandwidth, which is defined as the number of bits transmitted per second, in b/s, or bps. In the product design of the DDR3 interface, the DDR3 read/write bandwidth is an indicator that the designer must consider. This article mainly introduces the EMIF parameter configuration of the Quartus FPGA platform and the process of testing the DDR3 read and write bandwidth. The FPGA device model is Cyclone 10 GX 10CX220YF780E6G, and the DDR3 particle model is Winbond W631GG6KB.
Table of contents
3 Read and write bandwidth test
1 EMIF IP Configuration
Before performing the EMIF DDR3 read and write bandwidth test, make sure that the EMIF DDR3 IP clock and timing parameters are configured correctly.
General -> Clocks tab, fill in the memory clock frequency Memory clock frequency, here fill in 933M, PLL reference clock frequency is 116.625MHz.
Memory -> Latency and Burst tab, set the Memory CAS latency and Memory write CAS latency values according to the DDR3 memory particle user manual.
The DDR3 memory model used here is Winbond W631GG6KB, and the tCK corresponding to 933M is 1.07ns. According to the manual, CL = 13, CWL = 9.
The Memory Timing parameters are as follows:
2 AMM interface
Quartus EMIF IP provides AMM (Avalon Memory-Mapped) interface for DDR3 data transmission. The AMM interface is defined as follows.
amm_ready plays the role of waitrequest_n, when the controller is in the busy state, the signal will be pulled low; amm_burstcount indicates the number of cycles of read/write burst transmission; the bit width of DDR3 granular data interface is 16bit, 8n-prefetch, so amm_writedata and amm_readdata The bit width is 16bit × 8 = 128bit.
For the timing diagram of reading and writing of AMM interface and other details, please refer to the Introduction to Avalon® Interface Specification on Intel's official website .
3 Read and write bandwidth test
In this design, DDR3 reads and writes using a fixed address burst method, and the size of amm_burstcount is fixed at 64. Each time, 64 data are written first, and then 64 data are read out.
At the same time, define two counters wr_data_cnt and rd_data_cnt, which are used to count the read and write data for a period of time. It is necessary to pay attention to the bit width of the counter to avoid overflow. Here the counter bit width is defined as 32bit, and the time interval is 200ms.
The VHDL design code is as follows,
process(sys_rst,sys_clk)
begin
if sys_rst = '1' then
pstate <= st_init;
buf_test_wr_req <= '0';
buf_test_rd_req <= '0';
test_wr_q <= (others => '0');
test_wr_mask <= (others => '0');
wr_cnt_scope <= (others => '0');
rd_cnt_scope <= (others => '0');
rd_err_cnt_scope <= (others => '0');
elsif rising_edge(sys_clk) then
if timeout_event = '1' then
wr_cnt_scope <= (others => '0');
rd_cnt_scope <= (others => '0');
rd_err_cnt_scope <= (others => '0');
end if;
case(pstate) is
when st_init =>
-- power on delay and initialization
if ddr_init_done = '1' then
pstate <= st_idle;
else
pstate <= st_init;
end if;
when st_idle =>
-- idle state
pstate <= st_test_write;
when st_test_write =>
-- pull up req and wait fot ack
if buf_test_wr_req = '1' and test_wr_ack = '1' then
pstate <= st_test_write_end;
buf_test_wr_req <= '0';
else
pstate <= st_test_write;
buf_test_wr_req <= '1';
end if;
when st_test_write_end =>
-- wait write ending
if test_wr_end = '1' then
pstate <= st_test_read;
else
pstate <= st_test_write_end;
end if;
test_wr_q(4*128-1 downto 3*128) <= DDR_DATA_PATTERN;
test_wr_q(3*128-1 downto 2*128) <= DDR_DATA_PATTERN;
test_wr_q(2*128-1 downto 1*128) <= DDR_DATA_PATTERN;
test_wr_q(1*128-1 downto 0*128) <= DDR_DATA_PATTERN;
test_wr_mask <= (others => '0');
if test_wr_rden = '1' then
wr_cnt_scope <= wr_cnt_scope + 1;
end if;
when st_test_read =>
-- pull up req and wait for ack
if buf_test_rd_req = '1' and test_rd_ack = '1' then
pstate <= st_test_read_end;
buf_test_rd_req <= '0';
else
pstate <= st_test_read;
buf_test_rd_req <= '1';
end if;
when st_test_read_end =>
-- wait read ending
if test_rd_end = '1' then
pstate <= st_idle;
else
pstate <= st_test_read_end;
if test_rd_rdvld = '1' then
rd_cnt_scope <= rd_cnt_scope + 1;
if test_rd_rdata(4*128-1 downto 3*128) /= DDR_DATA_PATTERN then
rd_err_cnt_scope <= rd_err_cnt_scope + 1;
elsif test_rd_rdata(3*128-1 downto 2*128) /= DDR_DATA_PATTERN then
rd_err_cnt_scope <= rd_err_cnt_scope + 1;
elsif test_rd_rdata(2*128-1 downto 1*128) /= DDR_DATA_PATTERN then
rd_err_cnt_scope <= rd_err_cnt_scope + 1;
elsif test_rd_rdata(1*128-1 downto 0*128) /= DDR_DATA_PATTERN then
rd_err_cnt_scope <= rd_err_cnt_scope + 1;
end if;
end if;
end if;
when others => NULL;
end case;
end if;
end process;The SignalTap debugging waveform is as follows:
Read bandwidth:
7533666 × 128bit × 1s/200ms = 4.822Gbps
Write bandwidth:
7653248 × 128bit × 1s/200ms = 4.898Gbps
It can be further calculated that when the burst transmission is 64, the read and write efficiency of DDR3 is about 32.56%.