In the previous content, the basic knowledge of AXI and DDR3 was described, and a test experiment of reading and writing BRAM with AXI IP core was also done. Next, we will combine these parts together to do an experiment of using the AXI IP core to test the read and write of DDR3. Because the timing of DDR3 is more complicated, we generally use the official MIG IP core provided by Xilinx to control DDR3. The previous section introduced the MIG IP core of the more commonly used Native interface, and this experiment is based on the AXI IP core. To read and write DDR3, so we are going to use the MIG IP core of the AXI interface this time. Its interface meets the AXI timing, so I won’t go into details here.
1 Configure the AXI IP core
After creating a new project, we configure an AXI4 IP core in the same way as in the second section. The operation is the same as before, and you can refer to the second section. Next, as before, create a new Block Design, and then add the configured AXI IP core to it.
2 Configure the MIG IP core
1. Click the + sign to add an IP core, then search for the MIG IP core, and then double-click to select this IP core.
2. After selection, such a MIG IP core will appear in the BD.
3. Double-click to configure it, this interface will open, click NEXT.
4. Click as shown in the figure to create a MIG IP core, and then check the AAXI4 interface. The number of controllers is 1 by default, and then click NEXT.
5. This page is to select the chip model we want to be compatible with, not here.
6. Here we select the control type as DDR3, and click NEXT.
7. The clock period is 2500ps. This 400M clock refers to the working clock of DDR3. MIG will generate this 400M clock for DDR3. It will also generate a 100M clock for our user interface according to the 4:1 rule. In step 3, we choose Components to represent the memory type we choose as memory particles. Because the board on my side is Da Vinci PRO, so I chose the fourth one in this way. It has two pieces of 256M*16 DDR3, so its total data bit width is 32 bits. You can choose according to your own board model. choose.
8. Because the data bit width of our AXI IP core is 32 bits, we also configure it as 32 bits here.
9. The input clock here is 200MHZ, which is the working clock of MIG IP core, and the burst type is sequential burst.
10. Configure according to the diagram, because we are using the internal clock of the FPGA, so we choose No Buffer, and the reset option is active low. The next two options are to reduce power consumption and some optimizations, and we will enable them.
11. The resistance here remains unchanged by default.
12. Choose to read in the existing pin configuration here, and it is too troublesome to rebind.
13. After reading the XDC file, click Verify, and click NEXT after the verification is successful.
14. The next step is to keep clicking NEXT until this step, choose to accept the agreement, and continue to go down.
15. Then there is some information, and the IP core is generated after checking.
3 Module connection using BD
As shown in the figure, connect the signals between all modules, and the clock wizard in it is used to generate the 200M clock input by MIG. Then F6 checks, and after the check is correct, the design is packaged to generate our .V file. The specific operation is to select our BD file, right-click and select Create HDL Wrapper to generate our .V file.
In this way, our design is ready, and the next step is to simulate our design. We use the simulation example given by XILINX official to modify it to our simulation environment.
4 Simulation environment
1. We right-click to select our MIG IP core, and then select Open IP Example Design.
2. At this time, the system will generate the test file of MIG IP core for us, and also generate a pair of small modules for us.
3. We create a new import folder under the root directory of the project, and then copy the files, as shown in the figure.
Then we add these files to the project.
4. Then change the example in sim_tb_top.v to our top layer, so that it can be used. We only need to generate a 100M input clock for the PLL input. Our read and write test starts after the MIG initialization signal init_calib_complete is pulled high.
In this way, our simulation stimulus has been successfully modified, and the results can be verified through the simulation waveform diagram.
5 Simulation Waveform Diagram
It can be seen that at about 107us, the initialization signal has been pulled high, and at the moment of 120us, we start the read and write test.
As can be seen from the figure below, the AXI read data channel has read the last data, and the test completion signal TX_DONE has also been pulled high. The ERRO_FLAG signal is not pulled high, indicating that the function is normal.
It can also be seen from the signal of the MIG physical interface that the function is correct.
This experiment is introduced here, mainly to discuss the process of using the AXI bus to interact with the memory.