On one. We have USB2.0 simultaneous read-write all debugging, including the use of CHIPSCOP crawl waveform, but USB2.0 functionality is by no means merely these, but based on this project, we only need these. So down what we want to explain DDR almost every large project to be used.
Specifically with regard to some of the basics of DDR, we own tuition. Ado. let's start.
Step 1: Create DDRIP. As shown below, DDR is in the MIG
Step Two: In this step, there are four options, namely to create a DDR, DDR comes with using XILINX, update existing DDR, DDR's name. Here we choose the first one to create a DDR, the name is not changed (this according to their own wishes), click Next
The third step: The following figure shows the mean, we selected target FOGA models, but also gives the current XILINX our selection of models compatible with some models, keep the default state here, not choice. Just click Next.
Step Four: shown below are DDR AXI interface standard type DDR. Block diagram below BANK1 and BANK3 is an external DDR, the specific choice depends on the development board you choose, look at the development board DDR is connected to that end. Because I am using a development board connected to the BANK1. So BANK1 select DDR3 SDRAM. Then click Next.
Step Five: frequency selection options here can be 3000-3300Ps this clock has two meanings, first: that the operating frequency of DDR chips, and the second: that IP CORE reference clock; Memery part: presentation development class you are using DDR3 chip on the corresponding models; Creat Custom Part: If you do not express your correspondence on board DDR model, you can create yourself, but more required parameters. Here we choose 3200PS, with my development board model corresponding to the DDR. Click Next.
Step Six: This step is inadequate to do any of the settings, then these settings in the main impedance setting on the development board, we just click Next.
Step Seven: This is the input and output we have to choose the DDR, port different modes. The following two unidirectional data sheet 32BIT read ports and four-way port shown in FIG writing, we choose here 64BIT of bidirectional read and write ports. Mapping order address while selecting a second row BANK, ROW, COLUMN, and then click Next.
Step eight: Select here Robin circulation in rotation to these ports. Click Next.
The ninth step; here is mainly input impedance configuration, select the first external resistor to match with, RZQ selection pin L6, ZIO pin selection C2 (select two pins according to their development board to select, in the DDR is connected to the pin with a pull-down resistor connected to two pins, respectively FPGA ONE CHIP TERM1 and FPGA ONE CHIP TERM2), is then added DEBUG signal, here was not added, is not enabled, the system the clock type to be based on its own development team, I have here is a single-ended clock. Click Next.
NEXT like the rest of the way, thus generating what we call the IP CORE.
It is to build hi eh Xi'an to emulate the magic of the examples provided,
Step 10: Follow these steps to build the project
Step Eleven: When TEST PASSED instructions that appear to build success.
OK completed!