[Baoyan Interview] Principles of Computer Composition

The blogger sorted out some questions related to the principles of computer composition during the summer vacation, for the purpose of interviewing for postgraduate research. In the process of sorting out, some other materials on the Internet were also used for reference, most of which are no longer available for reference. If there is any infringement, we will notify you to delete it.
Because the accounting team was not asked much during the interview, so it was sorted out less. Only 2 times the teacher asked about the von Neumann architecture.

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1. The concept of von Neumann machine and stored program?

The idea of ​​"stored program" has established the basic structure of modern computers. All kinds of computers based on this concept are generally called von Neumann machines, and their characteristics are as follows:

1. The computer hardware system is composed of five major components: arithmetic unit, memory, controller, input device and output device.
2. Instructions and data are stored in memory on an equal footing and can be accessed by address.
3. Both instructions and data are represented in binary code.
4. An instruction is composed of an operation code and an address code. The operation code is used to indicate the nature of the operation, and the address code is used to indicate the location of the operand in the memory.
5. Instructions are stored sequentially in memory. Usually, instructions are executed sequentially, and the execution sequence can be changed according to the operation result or according to the set conditions under certain conditions.
6. The early von Neumann machine was centered on the arithmetic unit, and the input/output device transmitted data through the arithmetic unit and memory. Modern computers are memory-centric.

The concept of "stored program" refers to inputting instructions into the computer's main memory in the form of codes in advance, then executing the first instruction of the program according to its first address in the memory, and then executing other instructions in the order specified by the program. until the end of program execution.

2. How does the computer work?

The working process of the computer is divided into the following three steps:

1. Load programs and data into main memory.
2. Convert source programs into executable files.
3. Execute instructions one by one from the first address of the executable file.

3. In computer system architecture, what is compilation? What is the explanation?

There are two ways of translation, one is compilation and the other is interpretation.
A program written in a compiled language needs a special compilation process to compile the program into a machine language file, such as an exe file, before it is executed.
Interpretation is different. Programs in interpreted languages ​​do not need to be compiled. They are translated only when the program is running. One sentence is translated and executed without generating the target program. In this way, the interpreted language needs to be translated every time it is executed, which is relatively inefficient.

.java file->compile->.class file, compiled into .class bytecode, .class requires jvm interpretation, and then interprets and executes. Java is very special. Java programs need to be compiled but not directly compiled into machine language, that is, binary language, but compiled into bytecode (.class) and then executed by interpretation. The class after the java program is compiled is an intermediate code, not an executable program exe, not a binary file, so an intermediary is needed to interpret the intermediate code during execution, which is the so-called java virtual machine (JVM).
The C language compilation process is divided into four steps:
1. From .c file to .i file, this process is called preprocessing, directly copy the header file contained in #include to hello.c; replace the macro defined by #defifine, At the same time, delete the useless comments in the code, etc.
2. From .i file to .s file, this process is called compiling
3, from .s file to .o file, this process is called assembly
4, from .o file to executable file, this process is called linking, and the translated The binary is bundled with the required library

4. Describe the instruction execution process?

The address of the first instruction in the program is placed in the PC, and the first instruction is taken out according to the PC. After decoding and execution steps, etc., the computer’s functional components are controlled to work together to complete the function of this instruction and calculate the value of the next instruction. address. Use the newly obtained instruction address to continue reading the second instruction and execute it until the end of the program. The following takes the fetch instruction (that is, fetches the operand in the storage unit indicated by the instruction address code and sends it to the ACC of the arithmetic unit) as an example to illustrate, and its information flow is as follows:

1. Instruction fetching: PC->MAR—>M—>MDR—>IR
   Fetch instructions to IR according to PC, send the content of PC to MAR, and send the content in MAR directly to the address line, and at the same time, the controller sends the read signal to the read/write signal According to the address and read signal on the address line, the main memory reads the instruction from the specified storage unit and sends it to the data line. The MDR receives the instruction information from the data line and transmits it to the IR.
2. Analysis instruction: OP(IR)—>CU
   instruction decoding and sending control signal. According to the operation code of the instruction in the IR, the controller generates corresponding control signals and sends them to different execution components. In this example, the IR is a fetch instruction, so the read control signal is sent to the control line of the bus.
3. Execution command: Ad(IR)—>MAR—>M—>MDR—>ACC
   fetch operation. Send the address code of the instruction in IR to MAR, and send the content in MAR to the address line, and at the same time, the controller sends the read signal to the read/write signal line to read the operand from the designated storage unit of the main memory, and send it to the MDR through the data line, and then Transfer to ACC.

5. The main performance indicators of the computer

(1) Machine word length
Machine word length refers to the number of bits of binary data that can be processed by a computer for an integer operation (that is, fixed-point integer operation).
(2) Data path bandwidth
Data path bandwidth refers to the number of bits that a data bus can transmit information in parallel at one time.
(3) Main memory capacity
(4) Operation speed
① Throughput and response time
Throughput: refers to the number of requests processed by the system per unit time.
Response time: Refers to the waiting time from when the user sends a request to the computer to when the system responds to the request and obtains the desired result.
② main frequency and CPU clock cycle.
CPU clock cycle: usually beat pulse or T cycle, that is, the reciprocal of the main frequency, which is the smallest time unit in the CPU, and each action requires at least 1 clock cycle.
Main frequency: The frequency of the internal clock of the machine.

6. Multi-level storage system

In order to solve the three mutual constraints of large capacity, high speed and low cost in the storage system, in the computer system, a multi-level memory structure is usually used. From top to bottom in the figure, the bit price is getting lower and the speed is getting lower and higher. Slow, the capacity is getting bigger and bigger, and the frequency of CPU access is getting lower and lower.
In fact, the hierarchical structure of the storage system is mainly reflected in the "Cache-main memory" level and the "main memory-auxiliary memory" level. The former mainly solves the problem of CPU and main memory speed mismatch, and the latter mainly solves the capacity problem of the storage system.

7. Semiconductor RAM

The main memory is implemented by DRAM, and the layer (Cache) that depends on the processor is implemented by SRAM. They are all volatile memories. As long as the power is cut off, the original stored information will be lost.
(1) The working principle of SRAM
(2) The working principle of DRAM
(3) The characteristics of read-only memory ROM Both
ROM and RAM support random access memory, and both SRAM and DRAM are volatile semiconductor memories. However, once there is information in ROM, it cannot be easily changed, and it will not be lost even if the power is turned off. It is a read-only memory in a computer system.

ROM devices have two significant advantages:

1. The structure is simple, so the bit density is higher than that of the readable and writable memory.
2. It is non-volatile, so it has high reliability.

8.Cache

Cache memory: The cache memory in the computer is a small but high-speed memory located between the CPU and the main memory DRAM, usually composed of SRAM.
The role of Cache: to increase the rate of CPU data input and output. Cache has small capacity but fast speed, and memory has low speed but large capacity.
Replacement algorithm: When the Cache generates an access miss, the corresponding data should be read into the CPU and Cache at the same time. But when the Cache is full of data, new data must replace (eliminate) some old data in the Cache. The most commonly used replacement algorithms are random algorithm, first in first out algorithm (FIFO) and least recently used algorithm (LRU).
Write operation: Because it is necessary to ensure that the data cached in the cache is consistent with the content in the memory, the write operation of the cache is more complicated. Commonly used methods include write-through method, write-back method, and tagging method.
Mapping method with main memory:
direct mapping: the main memory data block can only be loaded into the unique location in the Cache
fully associative mapping: the main memory data block can be loaded into any location in the Cache
group associative mapping: the Cache is divided into Several groups, a data block can be loaded into any position in a group

9. Virtual memory

Concept : virtual memory refers to a memory system that can logically expand the memory capacity with the functions of request transfer and replacement

Virtual paging memory : paging management: the virtual storage space and the actual space are divided into fixed-size pages, and each virtual page can be loaded into a different actual page location in the main memory. In paging storage, the logical address of the processor is determined by the virtual The page number and the address in the page are composed of two parts, and the actual address is also divided into two parts: the page number and the address in the page. The address mapping mechanism converts the virtual page number into the actual page number of the main memory. A page table is used for page management,
including Page number, the starting position of each page in main memory, loading bits, etc. The page table is a mapping table between virtual page number and physical page number. Page management is performed by the operating system and is transparent to application programmers.

Segmented virtual memory : Segmented management: A storage management method that allocates main memory by segment. It is a modularized storage management method. Each user program module can be divided into a segment, and the program module can only access the segment assigned to it. The main memory space corresponding to the segment of this module. The segment length can be set arbitrarily, and can be enlarged and reduced. The
system uses a segment table to indicate the position of each segment in the main memory. The segment table includes the segment name (segment number) , segment starting point, loading position and segment length, etc. The segment table itself is also a segment. The segment is generally divided into program modules.

Segment page virtual memory : segment page management: it is a combination of the above two methods. It divides the storage space into segments according to logical modules, and each segment is divided into several pages. Memory access is performed through a segment table and several page tables. The length of a segment must be an integer multiple of the page length, and the start of a segment must be the start of a page.

TLB (fast table) :
When address translation is performed in virtual memory, the process of internal address translation from virtual page number to real page number in main memory is required.
When caching, you must first look up the page table in the main memory, and then you can access the access instructions or data in the main memory according to the physical address of the main memory. Therefore, after adopting the virtual memory mechanism, the number of memory accesses increases. In order to reduce the number of memory accesses, the most active page table entries in the page table are often copied to the cache. This kind of page table entry in the cache is called a fast table (translation look aside buffer)

10. Instruction pipeline

Basic concept : After the instruction fetch is completed, the next instruction can be fetched without waiting for the instruction to be executed. It is divided into fetching, decoding, executing, accessing memory, and writing back.

Instruction pipeline features :

1. Decompose a task (an instruction or an operation) into several related subtasks, each subtask is executed by a dedicated functional unit, and rely on multiple functional units to work in parallel to shorten the execution time of the program.
2. There must be a buffer register, or a latch, behind each functional section of the pipeline. Its function is to save the execution result of this pipeline section and supply it to the next pipeline section.
3. The time of each functional section in the pipeline should be as equal as possible, otherwise it will cause blockage and flow interruption.
4. Only when the same task is provided continuously can the efficiency of the pipeline be exerted, so the processing in the pipeline must be continuous tasks. In a processor that works in a pipeline, it is necessary to provide continuous tasks for the pipeline in terms of software and hardware design.
5. A pipeline needs to have a load time and an empty time. The load time is the time from the first task entering the pipeline to the output pipeline. Drain time is the time from the last task entering the pipeline to the time it exits the pipeline.

Factors affecting pipeline performance
1) Structural correlation is when multiple instructions compete for the same resource at the same time to form a conflict
Solution: (1) Pause for one clock cycle (2) Set data memory and instruction memory separately
2) Data correlation is that instructions are in the pipeline During overlapping execution, it occurs when the subsequent instruction needs to use the execution result of the previous instruction.
Solution: (2) Pause for one clock cycle (2) Data bypass: directly input the ALU calculation result of the previous instruction to the next one Instruction
3) Control correlation is caused when the pipeline encounters branch instructions and other instructions that change the PC value.
Solutions: (1) Delay transfer technology. Swap the transfer instruction with one or several instructions before it that have nothing to do with the transfer instruction, so that the successful transfer always occurs after the execution of the following instruction, so that the prefetched instruction will not be invalidated. (2) Transfer prediction technology.

11. Comparison between CISC and RISC

12. CPU function

The central processing unit (CPU) consists of arithmetic units and controllers. Among them, the function of the controller is responsible for coordinating and controlling the instruction sequence of each component of the computer to execute the program, including fetching instructions, analyzing instructions and executing instructions; the function of the arithmetic unit is to process data.
Specific functions of the CPU include:

1. command control . Complete the operations of fetching instructions, analyzing instructions, and executing instructions, that is, the sequence control of the program.
2. operational control . The function of an instruction is often realized by the combination of several operation signals. The CPU manages and generates the operation signals for fetching each instruction from the memory, and sends various operation signals to the corresponding components, so as to control these components to act according to the requirements of the instructions.
3. time control . Time control of various operations. Time control should provide proper control signals for each instruction in time sequence.
4. data processing . Perform arithmetic and logical operations on data.
5. Interrupt handling . Handle abnormal situations and special requests that occur during computer operation.

13. Bus

What is a bus:
a public communication trunk that transmits information between various functional components of a computer.

Why bus is needed:
1) The system structure is simplified, which is convenient for system design and manufacture.
2) The number of connections is greatly reduced, which is convenient for wiring, reduces the volume, and improves the reliability of the system.
3) It is convenient for interface design, and all devices connected to the bus adopt similar interfaces.
4) It is convenient for system expansion, update and flexible configuration, and Yiqian realizes the modularization of the system.
5) It is convenient for the software design of the equipment, and the software of all interfaces operates on different interface addresses.
6) It is convenient for fault diagnosis and maintenance, and can also reduce costs.

Bus-related concepts:
1. According to the different transmission information, what are the types of system bus? Is it one-way or two-way?
1) Divided into data bus, address bus and control bus.
2) Data bus: transfer data information between functional components, two-way transmission;
3) Address bus: used to indicate the address of the main memory unit where the source data or destination data is located on the data bus. One-way: issued by the CPU
4) Control bus: used to send various control signals. For a single line in the control bus, it is unidirectional, that is, it can only be sent from one component to another. In a group of control buses, there are inputs and outputs, so the control bus can also be regarded as bidirectional.

2. What are bus width, bus bandwidth, bus multiplexing, and number of signal lines?
1) Bus width: the number of data buses, generally a multiple of 8. It is an important index to measure the performance of computer system;
2) Bus bandwidth: that is, the bus data transmission rate, the maximum amount of bytes per second that can be transmitted on the bus.
3) Bus multiplexing: two signals are transmitted on one signal line in time division. For example, the time-division multiplexing of the data bus and the address bus;
4) The number of signal lines: the sum of the lines of the address bus, data bus and control bus.

14. What is the relationship between the three concepts of vector interrupt, interrupt vector, and vector address?

1) Interrupt vector : Each interrupt source has a corresponding handler. This handler is called an interrupt service routine, and its entry address is called an interrupt vector. The entry addresses of all interrupted interrupt service routines form a table, which is called the interrupt vector table; some machines also form a table with the jump instructions of the interrupt service routine entry, called the interrupt vector jump table.
2) Vector address : the memory address or index value of each entry in the interrupt vector table or interrupt vector jump table, which is called the vector address or interrupt type number.
3) Vector interrupt : refers to a technology or method for identifying interrupt sources. The purpose of identifying the interrupt source is to find the address of the entry address of the interrupt service program corresponding to the interrupt source, that is, to obtain the vector address.

15. What is the difference between program interruption and calling a subroutine?

The fundamental difference between the two is mainly reflected in the service time and service objects.
1) The time when the process of calling the subroutine is known and fixed, that is, when the call command (CALL) in the main program is executed, the process of calling the subroutine by the main program occurs, and the location of the call command is known and fixed. The time when the interrupt process occurs is generally random. When the CPU receives an interrupt application from the interrupt source when executing a certain main program, the interrupt process occurs. The interrupt application is generally generated by the hardware circuit, and the application time is random. It can also be said that the calling of the subroutine is arranged by the programmer in advance, while the execution of the interrupt service routine is randomly determined by the system working environment.

2) The subroutine completely serves the main program, and the two belong to the master-slave relationship. When the main program needs the subroutine, it will call the subroutine, and bring the calling result back to the main program to continue execution. The interrupt service routine and the main program are generally irrelevant, and there is no question of who serves whom, and the two are in parallel.

3) The process of the main program calling the subroutine is entirely a software processing process and does not require special hardware circuits; while the interrupt processing system is a combination of software and hardware, it needs special hardware circuits to complete the interrupt processing process.

4. Several levels of subroutine nesting can be realized, and the maximum number of nesting levels is limited by the stack size opened by the computer memory; while the number of interrupt nesting levels is mainly determined by the interrupt priority, and the general priority level is not very large.