Clock cycle : The smallest unit of time in a computer, equal to the reciprocal of the CPU's main frequency. In one clock cycle, the CPU only completes one of the most basic actions.
Machine cycle (CPU cycle) : In order to facilitate management in the computer, the execution process of an instruction is often divided into several stages (such as fetching, indirect addressing, execution, interrupt, etc.) and each stage
completes a basic operation. Note: Each basic operation is composed of several CPU's most basic actions. The time required for this basic operation is called a machine cycle, and a machine cycle consists of several clock cycles.
Instruction cycle : The total time required from the start of instruction fetching to the completion of execution of the instruction. An instruction cycle consists of several machine cycles.
Thus, instruction cycle > machine cycle > clock cycle .
Bus cycle : The memory and I/O ports are connected to the bus, and the CPU's access to the memory and I/O interfaces is realized through the bus. The time required for the CPU to access the outside of the microprocessor (memory or I/O interface) through the bus is called a bus cycle.
The bus cycle generally includes 4 bus clock cycles:
(1) T1 state - output memory address or I/O address.
(2) T2 state - output control signal.
(3) T3 and Tw states - the bus operation continues, and READY is detected to determine whether to extend the sequence.
(4) T4 state - complete data transmission.
Storage period : Storage period includes access time and recovery time. Refers to the minimum interval between two independent memory access operations.
Access time refers to the time elapsed from the initiation of a memory operation to the completion of the operation.
Recovery time refers to the time it takes to restore the internal state after a read or write operation.
The process of CPU memory access : the CPU sends the data address to the memory through the bus. After the memory gets the address, it starts the memory and prepares the data. The CPU outputs control signals or other operations until the data is ready. Then it is sent back to the CPU by the bus. A storage cycle is the time interval between two access operations to the memory. This time interval can contain multiple bus transfer cycles, because an access operation does not necessarily read data of a data bus width, so an access cycle can contain multiple bus transfer cycles,
Therefore, usually the storage cycle>bus cycle, the cpu cannot continuously access data and must wait.
In order to improve the transmission efficiency, two concepts are also introduced:
bus burst transmission mode : that is, the bus can transmit an address and a batch of data with continuous addresses in one bus cycle, instead of one address and one data in conventional transmission.
Multi-body parallel memory : The memory is composed of multiple memory modules, and the data is prepared in a pipelined manner, thereby increasing the memory bandwidth and shortening the data preparation time.