1. LT9211 chip overview
The LT9211 can implement single MIPI DSI/CSI-2 or single/dual LVDS or TTL video signals between
except for the conversion between 24-bit TTL to 24-bit TTL or between two sets of external synchronous TTLs, the maximum supported
200MHz pixel clock, generally 1920x1200 and below resolutions can be supported. In addition, the LT9211 also supports
Applications such as MIPI one-to-two, MIPI extension, etc. U5 version can support RAW data extension of CSI continuous clock.
See the LT9211 datasheet for details.
2. LT9211 Hardware Design Description
2.1 MIPI
MIPI input has two channels, but we only support 1-channel MIPI input, so A and B channels are optional
First, pay attention to the line sequence and positive and negative. It is not recommended to change the line sequence. If it is really necessary, you can configure it through code
lane swap. In terms of MIPI output, LT9211 can output 2port exactly the same MIPI signal, other
Same as MIPI input. MIPI input signal requirements are: Video mode (command mode is not supported), it is recommended
Turn off spread spectrum. In addition, MIPI repeater supports RAW format input.
2.2 LVDS
Support single/dual-channel LVDS, single-channel LVDS maximum support 100MHz pixel clock, two-channel maximum support
200MHz, pay attention to the line sequence and positive and negative, it is not recommended to change the line sequence, if necessary, you can configure it through the code
Set lane swap. The A and B channels of 2port LVDS can be exchanged by code, and the default is A odd and B even.
LVDS does not support YUV format, LT9211 only supports LVDS in RGB format.
2.3 TTL
BT1120/BT656 and other internal synchronization signals do not have HS, VS, DE signal lines, while RGB is an external synchronization signal.
Need to connect HS, VS, DE signal. LT9211 uses GPIO0-GPIO7 as D0-D4, HS, VS, DE.
RGB565, RGB666 should be suspended in the low position, connect to the high position of each group
2.4 Other considerations
The LT9211 crystal oscillator uses an external passive 25MHz (25MHz±20ppm) crystal oscillator, which cannot be changed at will
Other frequencies or active crystal oscillators.
The external resistor REXT is used to match the internal reference current of the chip, and a 6.04K±1% precision resistor is selected, the same as
The resistance value cannot be changed arbitrarily.
VCCIO is connected to 1.8V when the input and output are MIPI/LVDS signals; the input or output contains TTL signals
, the VCCIO and TTL levels remain the same. VCCIO has nothing to do with I2C, reset, INT and other levels,
I2C, RESET, INT are all 1.8V or 3.3V pull-up compatible.
The LT9211 requires an external MCU, master or other I2C master to be controlled via I2C, the reference MCU is new
Tang N76E003, if you choose the reference MCU, you don’t need to transplant the code, just burn the hex firmware to the MCU;
If you choose other MCU or main controller to control, you need to transplant the code by yourself, and connect 0Ω in series on the I2C channel
Resistor, convenient for subsequent debugging with MCU.
3. Software configuration instructions
0. All software debugging is carried out on the basis that there is no problem with the hardware, so it is necessary to check the hardware before debugging.
software principle .
1. What parameters need to be changed for MIPI input?
1.1 MIPI lane number: register 0xd000
HDMI_WriteI2C_Byte(0xff,0xd0);
HDMI_WriteI2C_Byte(0x00,MIPI_LANE_CNT); // 0: 4 Lane / 1: 1 Lane
/ 2 : 2 Lane / 3: 3 Lane
1.2 MIPI CSI input setting
The default is DSI configuration, adding the following configuration is the CSI input setting:
HDMI_WriteI2C_Byte(0xff,0xd0);
HDMI_WriteI2C_Byte(0x04,0x10);
//bit4-enable CSI mode
HDMI_WriteI2C_Byte(0x21,0xc6);
1.3 MIPI RX PLL : set according to the clock, dessc pll is an automated module
HDMI_WriteI2C_Byte(0xff,0x82);
HDMI_WriteI2C_Byte(0x2d,0x48);
if((video_format->pclk_khz) < PCLK_KHZ_44000)
{
HDMI_WriteI2C_Byte(0x35,PIXCLK_22M_44M);/*0x83*/
}
else if(video_format->pclk_khz < PCLK_KHZ_88000)
{
HDMI_WriteI2C_Byte(0x35,PIXCLK_44M_88M); /*0x82*/