Special Note
1. The maximum input HDMI supports 3840x2160P30hz, supports RGB888/YUV444/YUV422/YUV420;
2. The output MIPI supports CSI and DSI, and supports RGB888/YUV444/YUV422/Y420.
The 420 format cannot be converted with other formats
. If YUV420 output is required,
Then the input must also be YUV420.
3. The calculation of MipiClock, LT6911C is calculated by Byteclk, MipiClock=4*Byteclk,
Mipi DataRate=2* MipiClock(DDR value),Byteclk >=(Pixclk*PixelBytes/LaneNum),
Among them, PixelBytes is the number of bytes occupied by each Pixel, such as RGB888/YUV44, then PixelBytes=3;
Another example is RGB565/YUV422, then PixelBytes=2. Take 4K30hZ HDMI input, single Port 4Lane CSI YUV422 output as an example, Pixclk=297Mhz,
Byteclk=(297*2/4)Mhz+5Mhz, general horizontal screen resolution Byteclk plus 5~10 to the theoretical value, vertical screen plus 10~20 to the theoretical value;
4. The input and output of LT6911C is Bypass mode, that is, whatever resolution and frame rate HDMI inputs, MIPI will output the same resolution and frame rate;
5. For
CSI applications
, be sure to connect GPIO5/Reset/CSC_IIC to the SOC. When the resolution changes, GPIO5 generates a 200mS high-level pulse, and the SOC reads the resolution through IIC, etc.
information;
6.
DSI application scenario 1
has audio requirements, when there is no valid signal GPIO5 outputs low level, and there is a stable signal output high level, the external MCU can control the screen through this signal
Power on and off sequence;
7.
If there is no audio requirement in
DSI application scenario 2 , the power on and off sequence of the screen can be controlled through Pin26/27/28/29;
8.
The IIC address description of the chip
, the device address is 0x56, where Bit0 is the read and write bit, and the upper 7 bits are the address bits.
Register address description
, the internal registers of the chip adopt 16-bit addressing (reading and writing operations are still consistent with 8-bit addressing), of which the upper 8 bits are the Bank address, and the lower 8 bits are the Bank internal bias
address. To access different bank registers, you need to switch the bank address first (the register storing the bank address is 0xFF), and then set the offset address. For example, read chipID register
device 0xa000/01, where the Bank address is 0xa0, and the offset address is 0x00/01;
10. External SOC or MCU needs to set
iic_enable(0x80ee=0x01) to access internal registers, and
iic_disable(0x80ee=0x00)
must be used to exit access
.
3. Software debugging and compiling
1. The timing configuration method, for HDMI, the corresponding timing value will be output according to the first DetailTiming of EDID
1.1. Modify the g_TimingStr structure and set g_EdidBlockCalEnable to TRUE;
The Lt6911_HdmiEdidSet function will replace the first DetailTiming of the default EDID according to EdidBlockCalEnable=TRUE.
1.2. Modify ONCHIP_EDID and set g_EdidBlockCalEnable to FALSE;
In this mode, the software will write the EDID of ONCHIP_EDID into EDID_Shadow of 6911C.
Pay special attention that the size of Hblank should not be less than 10% of Havtive, 15% is recommended, for example, 1200x1920, hs+hbp+hfp=180
2. Modify mipi format
g_ChipModel = LT6911C;/
/LT6911C
&
LT6911
According to the chip signal selection, double mipi chooses LT6911C, four mipi chooses LT6911
g_DisplayMode = VideoCopyMode; //
VideoCopyMode
&
SideBySideMode
VideoCopyMode means dual mipi output the same content, SideBySideMode means double mipi left and right splicing output;
g_OutputMode = YUV422;//
RGB
&
YUV422
&
YUV444
Generally, DSI chooses RGB, CSI chooses YUV422, and chooses according to the required format;
g_MipiFormat = YUV422_8bit;//RGB888 & YUV422_8bit
Generally, DSI chooses RGB888, and CSI chooses YUV422
g_MipiType = CSI;//DSI & CSI
3. Modify mipi videomode and lane number
MIPI g_MipiSetStr =
{
Port_4lane//
Port_4lane
&
Port_3lane
&
Port_2lane
&
Port_1lane
, Burst_Mode//
Burst_Mode
&
NonBurst_SyncPulse_Mode
&
NonBurst_SyncEvent_Mode
, NonContinuousClock//
ContinuousClock
&
NonContinuousClock
};
3.1,
Port_4lane
&
Port_3lane
&
Port_2lane
&
Port_1lane
represent 4, 3, 2, 1lane mipi selection, configure according to actual needs,
This initial configuration is for all ports, that is, the mipi lanes of different ports must be the same.
3.2, Video Mode, there are four combinations, the common combination is
Burst_Mode + NonContinuousClock
Combination 1,
Burst_Mode + ContinuousClock
Combination 2,
Burst_Mode + NonContinuousClock
Combination 3,
NonBurst_SyncPulse_Mode + ContinuousClock
Combination 4,
NonBurst_SyncEvent_Mode + ContinuousClock
4. Modify GPIO5 and IIS_gpio
#define GPIO5_LCDReset
0
// dsi is set to 1, csi is set to 0, the purpose is whether GPIO5 only interrupts or resets the lcd
#define IIS_GPO
0
//iis is set to 1 for GPO and 0 for audio output
5. Fine tune mipi clk
The OFFSET constant in the function Lt6911_MipiClockSet, this function is used to configure Bytclk or byte clock, MIPI clk=4* wr_byteclk;
6. Fine tune mipi dphy parameters
For the function Lt6911_MipiDphySet, the key parameters are the time of lp and prep, and the unit is one cycle of Byteclk. Fine-tuning only needs to be on the right side of the equation +
A constant within 5 is enough;
wrhslpx = rdbyteclk/20 ; // hs lpx > 50ns
wrhsprep = rdbyteclk/18 + 2 ; //hs prep : (40ns + 4*UI)~(85ns + 6*UI)