Detailed IIC bus

Detailed IIC bus protocol

One, IIC introduction and performance indicators:

1. There are two kinds of working speed: 100K and 400K;

2. Support multi-machine communication;

3. Support multiple main control modules, but only one main control is allowed at the same time;

4. Serial bus composed of data line SDA and clock SCL;

5. Each circuit and module has a unique address;

6. Each device can use independent power supply (must be common ground to maintain stability)

2. The basic working principle of IIC:

1. Use the start signal START to control the bus, and the stop signal STOP to release the bus;
2. Each communication starts with START and ends with STOP;
3. Immediately after the start signal START, an address byte is sent, of which 7 bits are the address code of the controlled device, one bit is the read/write control bit R/W, and the R. /W bit is 0, which means that the master is to the controlled device Write data, R/W is 1 means that the master reads data to the controlled device;
4. When the controlled device detects that the received address is the same as its own address, it will feedback a response signal during the 9th clock period;
5. Each data byte is high-order (MSB) first during transmission;

Three, IIC communication process

• Write communication process:

1. When the master detects that the bus is idle, it first sends a START signal to control the bus;
2. Send an address byte (including 7-bit address code and one R/W);
3. When the controlled device detects that the address sent by the master is the same as its own address, it sends an acknowledge signal (ACK);
4. After the master receives the ACK, it starts to send the first data byte;
5. After receiving the data byte, the controlled device sends an ACK to indicate the continued data transmission, and a NACK indicates the end of the data transmission;
6. After the master sends all the data, it sends a stop bit STOP to end the entire communication and release the bus;

• Read communication process:

1. When the master detects that the bus is idle, it first sends a START signal to control the bus;
2. Send an address byte (including 7-bit address code and one R/W);
3. When the controlled device detects that the address sent by the master is the same as its own address, it sends an acknowledge signal (ACK);
4. After receiving the ACK, the master releases the data bus and starts to receive the first data byte;
5. After the master receives the data, it sends an ACK to indicate the continued data transmission, and sends a NACK to indicate the end of the data transmission;
6. After the master sends all the data, it sends a stop bit STOP to end the entire communication and release the bus;

Four. Bus signal timing analysis (emphasis)

1. Bus idle state
   SDA and SCL two signal lines are both at high level, that is, all devices on the bus release the bus, and the pull-up resistors of the two signal lines pull the level high; send during the 9th pulse of the clock The receiver releases the data bus, and the receiver does not pull down the data bus to indicate a NACK. NACK has two purposes:
   a. Generally, it indicates that the receiver has not successfully received data bytes;
   b. When the receiver is the master, it receives the last After one byte, a NACK signal should be sent to notify the controlled transmitter to end data transmission and release the bus so that the master receiver can send a stop signal STOP.

2. Start signal START

   The clock signal SCL maintains a high level, and the level of the data signal SDA is pulled low (ie, a negative transition). The start signal must be a jump signal, and it must be repaired before establishing the signal to ensure that the bus is in an idle state;

3. Stop signal STOP

   The clock signal SCL maintains a high level, and the data line is released, so that SDA returns to a high level (that is, a positive transition), and the stop signal must also be a transition signal.

4. data transmission

   During the high level of the SCL line, the level on the SDA line must remain stable, low level means 0 (the line voltage at this time is the ground voltage), high level means 1 (the voltage at this time is determined by the VDD of the component ). Only when the SCL line is low, the level on SDA is allowed to change.

5. ACK

   The data of the I2C bus is transmitted in bytes (8 bits). After the sending device sends a byte, the data bus is released during the 9th pulse of the clock, and the receiver sends an ACK (to transfer the data bus The level is pulled low) to indicate successful data reception.

6. No response signal NACK

V. Addressing Conventions

There are two ways to allocate addresses:

   1. 含CPU的智能器件，地址由软件初始化时定义，但不能与其它的器件有冲突；
   2. 不含CPU的非智能器件，由厂家在器件内部固化，不可改变。

The upper 7 bits are the address code, which is divided into two parts:

1. The upper 4 bits belong to the fixed address, which cannot be changed, and is a unified address fixed by the manufacturer;
2. The lower three bits are the pin setting addresses, which can be set by external pins (not all devices can be set);

The lowest bit is the read and write operation code:

1. 0 means writing data to the target address bus
2. 1 means reading data to the target device