The chip MPU-6050 chip driver of the three-axis gyroscope uses the IIC bus protocol to communicate with the processor. Learn about the protocol of the IIC bus and summarize it here:
The communication between the processor and the chip can be likened to two people speaking: 1. What you say must be understood by others: the agreement between the two parties to agree on the signal. 2. Your speaking speed must be acceptable to others: both parties meet the timing requirements.
Look at the IIC protocol first: two lines can hang multiple devices. The IIC device (slightly smarter) has a fixed address in it. I only respond if the value transmitted on both lines is equal to my (IIC device) address.
Start signal: The processor keeps the SCL clock high, and then changes the SDA data signal from high to low to indicate a start signal. At the same time, when the device on the IIC bus detects this start signal, it knows that the processor is going to send data.
Stop signal: The processor keeps the SCL clock high, and then changes the SDA data signal from low to high to indicate a stop signal. At the same time, when the device on the IIC bus detects this stop signal, it knows that the processor has ended the data transmission, and we can work on each of them, such as sleep.
Let's look at The data on SDA can only be toggled during the period when SCL is low.
Response signal (ACK): The processor sends data to the external IIC device, how to know that the IIC device data has been received? An external IIC device is required to respond with a signal to the processor. After the processor sends 8bit data, it will no longer drive the bus (the SDA pin becomes an input), and both SDA and SDL hardware are designed with pull-up resistors, so SDA becomes high at this time. Then in the 8th data bit, if the external IIC device can receive the signal, then SDA is pulled low in the 9th cycle, then the processor detects that the SDA is pulled low to know that the data of the external IIC device has been received.
IIC data is transmitted from the most significant bit.
Going a step further: The IIC bus allows multiple devices to be mounted. How to access one of the devices without affecting other devices?
If 7bit is used to represent the slave address, then the number of slave devices that can be mounted is 2 to the 7th power of 128. If the processor wants to write: first send the start bit, and then send an 8bit data: the first 7bit represents the slave address, and the 8th bit represents read or write. 0write is sent by the processor to the IIC slave device, and 1read is sent from the IIC slave device to the processor. The ninth clock cycle replies to the response signal.
Let's take AT24Cxx as an example to explain in detail:
First issue a start signal,
Slave address, R/W (0, write),
A response of ACK indicates that the slave device exists.
Specify the 8bit/16bit access address in the slave device.
ACK response with this address
Continue a start signal + slave device address, the lowest bit is a high level to indicate read data, and an ACK response indicates that the slave device exists.
When reading data, each time a clock is issued, the processor will store the data on the SDA. Then the processor can get 8-bit data after sending 8 clocks. At this time, if you want to read continuously, you will continue to respond to the ACK signal, otherwise a stop signal will be issued.
The process of reading: start signal, slave device address, write, storage address to be read, another start signal, slave device address, read, 8 clocks, and the slave device will feed back the corresponding data to the processor.
start signal, which device address, write, followed by two consecutive bytes of data: the address to be written, the other party responds with ACK after receiving the 8bit address, and then sends the 8bit data to the slave device, and the other party responds after receiving the 8bit data ACK, the processor sends a stop signal after writing.