1 What is the AXI bus?
AXI (Advanced eXtensible Interface) is a bus protocol. This protocol was not proposed by Xilinx, but is the most important part of the AMBA (Advanced Microcontroller Bus Architecture) 3.0 protocol proposed by ARM. The latest AXI4 bus was released in AMBA4.0 version in 2010.
2 AXI is divided into several types
The AXI4 bus protocol has three types of interfaces:
(1) AXI4: Standard AXI4 bus type, which is an address mapping-oriented interface that supports burst transmission of data and allows a maximum data burst length of 256 clock cycles. This interface is mainly oriented to the needs of high-performance address mapping communication.
(2) AXI4-Lite: It is a lightweight address mapping single transmission interface. It only supports a single data transmission each time. Since it has fewer functions, it takes up less resources. This protocol is suitable for small throughput. The address maps the communication bus.
(3) AXI4-Stream: As the name suggests, it is a form of streaming media transmission. This protocol removes the address transmission function and allows unlimited data burst transmission without the need for address mapping. It is mainly aimed at high-speed data transmission.
3 AXI working mode
3.1 AXI channel description
The AXI bus is divided into 5 channels, namely read address channel, read data channel, write address channel, write data channel and write response channel.
(1) Read address channel (AR channel): contains ARVALID, ARADDR, ARREADY signals;
(2) Read data channel (R channel): contains RVALID, RDATA, RREADY, RRESP signals;
(3) Write address channel (AW channel) : Contains AWVALID, AWADDR, AWREADY signals;
(4) Write data channel (W channel): Contains WVALID, WDATA, WSTRB, WREADY signals; (
5) Write response channel (B channel): Contains BVALID, BRESP, BREADY signals;
due to AXI4-Stream does not need to be mapped by address, so the interface components of the AXI4-Stream bus are:
(1) ACLK signal: bus clock, valid on rising edge;
(2) ARESETN signal: bus reset, valid on low level;
(3) TVALID Signal: The host tells the slave that the data transmission is valid;
(4) TREADY signal: The slave tells the host to prepare for transmission; it should be noted that only when the TVAILD and TREADY signals are high at the same time, the handshake is successful. transfer data.
(5) TLAST signal: The master tells the slave that this transmission is the end of the burst transmission; when TLAST is high, it indicates that the current data is the last transmission.
(6) TDATA signal: data, optional width 32, 64, 128, 256bit;
(7) TKEEP signal: similar to byte modifier, indicating that the data is valid.
(8) TSTRB signal: Each bit corresponds to a valid byte of TDATA, and the width is TDATA/8;
(9) TUSER signal: user-defined signal with a width of 128 bits.
3.2 AXI bus data transmission implementation process
3.2.1 Data reading implementation process
The figure below is a schematic diagram of the flow chart of reading data. From the above content, if there is any doubt as to why there is no reading feedback signal when reading data, we can draw conclusions from this schematic diagram. When the master sends an address to the slave and the slave sends data to the master, the feedback signal is actually included.
The host gives the address and control information of the data to be read on the read address channel (when reading multiple data in a burst, the first address of data storage and the burst length are given), and the slave passes the data after receiving it. Read data channel sent to host.
3.2.2 Writing data implementation process
The figure below shows the way a write transaction uses write address, write data and write response channels. The host first sends write control to the host, and then sends the data to be written. The slave gives the write control after receiving the data of this write transaction. The response signal represents the completion of reception.
3.2.3 AXI4 handshake mechanism
There are three situations in the handshake mechanism: the valid signal arrives first, the ready signal arrives first, and the two signals arrive at the same time. The following is a detailed analysis of these three situations:
The VALID signal arrives first.
The timing diagram is as shown in the figure below:
the source device gives address, data or control information after the T1 moment (white indicates useful), and the VALID signal becomes useful after the T1 moment. At the rising edge of the clock at time T2, the system knows that the information is valid. The target device sends the ready signal after time T2 and misses the rising edge of time T2. Therefore, the source device must keep the information it carries stable until time T3. At this time, the handshake signals are all high level and the information begins to be transmitted. The actual transmission occurs. It is the rising edge at T3 time.
The source must wait for the READY signal to be valid after making the VALID signal valid. Once VALID is valid, the source must wait for the handshake to occur, that is, while keeping the VALID unchanged, wait for the READY signal of the destination to be valid. The high and low levels of VALID are not determined by the READY signal, but only by the usefulness of the information.
The READY signal arrives first.
The timing diagram is shown in the figure below:
At this time, the READY signal starts to pull high after T1, and at T2 the system begins to know that the target device is ready. After T2, the address, data or control information is given, and VALID becomes valid. After T3, the handshake is completed and data transmission begins. Here we can see that the target device can actually keep the READY signal high, because as long as there is space in the target device register. This can be distinguished from the first case. The first case is that whether the VALID signal is high or low actually depends entirely on whether the signal is useful. At this time, if VALID is high first, the handshake must be completed before it can be pulled back. However, in this case, before VALID is valid, even if READY is already valid, READY can be invalidated again. READY's pull-high and pull-low standards depend on the target device and have nothing to do with VALID.
Two signals arrive at the same
time. The timing diagram is shown in the figure below:
In this case, the VALID/READY signals at both ends are valid at the same time, and the transmission starts immediately in the next clock cycle.