The SPI (Serial Peripheral Interface) bus system is a synchronous serial peripheral interface that allows the MCU to communicate with various peripheral devices in a serial manner to exchange information. This interface generally uses 4 lines: the serial clock line (SCLK ), master-in slave-out data line (MISO), master-out slave-in data line (MOSI) and low-level active slave select line (SS); its main features include: it can send and receive ship type data at the same time; it can be used as Master or slave work; send end interrupt flag; write conflict protection and bus contention protection.
Schematic diagram of SPI bus architecture:
SPI is a ring bus structure, consisting of SS, SCK, SDI, and SDO. It performs bidirectional transmission between the master device and the slave device to send and receive data, with a maximum rate of 5Mbps. The slave device for master device communication is selected by the SS signal. At a certain point in time, point-to-point communication can be achieved between the master device and the slave device without the need for addressing operations. There are 4 working modes of SPI, SP0, SP1, SP2, SP3, among which SP0 and SP3 are more commonly used. In order to exchange data with peripherals, the polarity and phase of its output serial synchronization clock can be set according to the working requirements of the peripherals.
If the clock polarity CPOL=0, the idle state of the serial synchronization clock is low level; if the clock polarity CPOL=1, the idle state of the serial synchronization clock is high level.
If the clock phase CPHA=0, the data is sampled on the first transition edge (rising or falling) of the serial synchronous clock; if the clock phase CPHA=1, the data is sampled on the second transition edge (rising or falling) of the serial synchronous clock. rising or falling) data is sampled. The clock phase and polarity of the SPI master module and the peripherals communicating with it should be consistent.
SCK diagram of working mode in SPI bus 4:
The main working sequence of SPI is under the control of SCK, two bidirectional shift registers perform data exchange.
Assume that the following 8-bit register contains the data to be sent 1010 1010. It is sent on the rising edge and received on the falling edge. The high bit is sent first. Then when the first rising edge comes, the data will be sdo=1, register = 0101 010x; when the falling edge comes, the level on sdi will be latched into the register, then the register = 0101 010sdi, so After 8 clock pulses, the contents of the two registers are exchanged with each other once, thus completing an SPI timing sequence.
Hardware SPI mode:
(1) Write a byte:
SPI_Writebyte(u8 data)
{ While (SPI_I2S_GetFlagStatus(SPI1,SPI_I2S_FLAG_TXE)==RESET);//Waiting for the send buffer to be empty SPI_I2S_SendData(SPI1,Data); While (SPI_I2S_GetFlagStatus( SPI1,SPI_I2S_FLAG_RXNE)==RESET);//Waiting to receive a byte of data SPI_I2S_ReceiveData(SPI1); } (2) Read a byte: SPI_Readbyte(u8 data) { While (SPI_I2S_GetFlagStatus(SPI1,SPI_I2S_FLAG_TXE)==RESET) ;//Waiting for the send buffer to be empty SPI_I2S_SendData(SPI1,Data);
While (SPI_I2S_GetFlagStatus(SPI1,SPI_I2S_FLAG_RXNE)==RESET);//Waiting to receive a byte of data
return SPI_I2S_ReceiveData(SPI1);
}
Analysis: When FIFO is not used, there is only one interrupt, one shared for reception and transmission, because sending and Reception is completed at the same time: for example, the master sends on the rising edge and receives on the falling edge, then the slave receives on the rising edge and sends on the falling edge. Therefore, after a series of clocks, the master has finished sending the data, and the slave has also finished sending the data.
Software SPI:
The difference between software SPI mode and hardware SPI mode:
1. Hardware SPI is more efficient. When writing a program, you only need to write the data to be sent into the register, and the hardware will automatically send it; software SPI needs to realize the clock pull-up and pull-down according to the timing. Serial data output, etc.
2. Hardware SPI must require the processor to support this function; while software SPI does not require specific requirements, general IO ports can be used.
3. Hardware SPI transmission speed can reach 3Mbps, and software SPI transmission speed is generally around 700K.
Summary: When using SPI, choose whether to use hardware SPI or software SPI according to the actual situation. Pay attention to ensuring the accuracy of the timing when using it.