quartus call & design D flip-flop-simulation & timing wave verification

table of Contents

1. Design a D flip-flop with gate circuit in Quartus-II, and perform simulation and timing waveform verification;
2. Directly call a D flip-flop circuit in Quartus-II for simulation and timing waveform verification, and do it with 2. Comparison;
3. Write a D flip-flop in Verilog language in Quartus-II for simulation verification

One, recognize the D flip-flop

D flip-flop is an information storage device with memory function and two stable states. It has a variety of configurations 时序电路的最基本逻辑单元and is also an important unit circuit in digital logic circuits.
D flip-flop 时钟脉冲CP的前沿（正跳变0→1）发生翻转, the second state of the flip-flop depends on the state of the D terminal before the CP pulse rising edge, that is 次态=D. Therefore, it has two functions of setting 0 and setting 1. Since the circuit has a blocking effect during CP=1, the data state of the D terminal changes during CP=1 and will not affect the output state of the flip-flop.
D flip-flops are widely used and can be used as digital signal register, shift register, frequency division and waveform generator, etc.

1. Structure

The D flip-flop (data flip-flop or delay flip-flop) consists of 4 NAND gates, among which G1 and G2 constitute the basic RS flip-flop. When level-triggered master-slave triggers work, the input signal must be added before the positive edge. If there is an interference signal at the input during the CP high level, then it is possible to make the state of the flip-flop wrong. The edge trigger allows the input signal to be added immediately before the CP trigger edge. In this way, the time for the input terminal to be disturbed is greatly shortened, and the possibility of being disturbed is reduced. Edge D flip-flops are also called sustain-blocking edge D flip-flops. The edge D flip-flop can be formed by connecting two D flip-flops in series, but the CP of the first D flip-flop needs to be reversed with a NOT gate.

2. Features

Function table

timing diagram

Here is a brief introduction to D flip-flops. For more understanding of D flip-flops, you can refer to the link below;
D flip-flops .

2. Design D flip-flop and timing verification

1. Create a project

file—>new project wizard

edit the project name, then click next to

select the appropriate chip and its series

The next

project is created directly , click Finish

2. Create a box file

Click the new

selection of the red block signature

by selecting icon

selection nand2, two-input NAND gate, and sequentially added 4 nand2 a NAND gate not

added after FIG

selected Wiring tool

connection shown in FIG effect (by double-clicking The pin name can be changed)

Save the circuit diagram

3. Compile the schematic file

Compile the circuit diagram

Compile the interface

rtl viewer, view the hardware circuit

diagram Circuit diagram

4. Create a vwm wave file

Select the icon vwm

operation as shown in the figure

Add node or bus

effect display

Edit input signal clk, generate clock signal

Select D, Q signal Q_n with the mouse, and edit (left mouse button to select and double click to change the value)

5. Timing waveform simulation

Compile

There is an error.

Connect modelsim


error report solution. The


result is shown in the figure.

Simulation result

Three, call D flip-flop and timing verification

1. Create a box file

The method of creating the project is the same as above.
Invoking the D trigger,

connecting to the pin, the effect is as shown in the figure (Ctrl+mouse wheel can zoom the trigger pin, etc.)

2. Compile the schematic diagram

View the hardware diagram

Compile

3. Create vwm waveform file and simulation

Waveform

Timing Simulation Results

Fourth, verilog language to achieve D flip-flop and timing verification

1. Write verilog files

First create the project, the method is the same as above.
Create a Verilog file, click file-new and

paste the following code

//demo是文件名
module demo(d,clk,q);
    input d;
    input clk;
    output q;

    reg q;

    always @ (posedge clk)//我们用正的时钟沿做它的敏感信号
    begin
        q <= d;//上升沿有效的时候，把d捕获到q
    end
endmodule

Save and compile

2. View the generated circuit diagram

3. Test timing simulation

code show as below

//测试代码
`timescale 1ns / 1ns

module demo_tb;
    reg clk,d;
    wire q;

    demo u1(.d(d),.clk(clk),.q(q));

    initial
    begin
        clk = 1;
        d <= 0;
        forever
        begin
            #60 d <= 1;//人为生成毛刺 
            #22 d <= 0;
            #2  d <= 1;
            #2  d <= 0;
            #16 d <= 0;//维持16ns的低电平，然后让它做周期性的循环
        end
    end

    always #20 clk <= ~clk;//半周期为20ns,全周期为40ns的一个信号
endmodule

Save and compile

simulation renderings

Five, summary and reference materials

1. Summary

During the process of D flip-flop and timing simulation, it can be found that the basic function of D flip-flop is that when the reset signal is 1, the rising edge of CLK will cause the Q value to change. From this, it can be concluded that the substate equation is Q n + 1 = D

2. Reference materials

Quartus II comes with the use of simulation tools .
Quartus-II input schematic and simulation
steps.docx . Quartus-II13.1 three ways to achieve D flip-flop and timing simulation .