Table of contents
1. Download the download and installation of Quartus II
1.2, Quartus II installation registration
Two Modelsim download and installation
Three design D flip-flop based on the gate circuit
Four call the D flip-flop circuit in Quartus-II
5 Realize D flip-flop based on Verilog language
1. Download the download and installation of Quartus II
1.1 Quartus II download
Baidu network disk download link:
Please enter the extraction code for Baidu Netdisk
Extraction code: ifte
1.2, Quartus II installation registration
Run the executable file after decompression, and then follow the steps to install, after the installation is complete
Download the crack file:
The cracker is displayed as follows, click "Exit"
Open Quartus II on the desktop,
After selecting "license setup" under "tools" , the following window will pop up, just copy the ID
After the last success:
The installation is complete.
Two Modelsim download and installation
2.1 Installation of Modelsim
Run the executable after decompression
2.2 Registration of Modelsim
1 Find the mgls64.dll file in the software installation directory, right-click the file and cancel the read-only attribute.
2 Copy MentorKG.exe and patch_dll.bat to win32 or win64 in the modelsim installation directory
3 Run patch_dll.bat to generate a license file, and put the license file in any directory, such as the win64 folder in the installation directory.
4 Set the environment variable name MGLS_LICENSE_FILE, and the variable value is the path where the license is placed.
Registration is complete
Three design D flip-flop based on the gate circuit
3.1 1. Create a project
3.2 Design gate circuit
Circuit elements: 4 and2
, 1 not
, 2 input
, 2output
3. Compile the simulation
Create vwm format wave file
Select CLK to generate clock signal
Select the D, Q signal Qn with the mouse to edit
Timing Waveform Simulation
Four call the D flip-flop circuit in Quartus-II
Use D flip-flops:
Simulation:
5 Realize D flip-flop based on Verilog language
Create a Verilog file:
Write Verilog code:
module D_Trigger(d,clk,q);
input d,clk;
output q;
reg q;
always @ (posedge clk)
if(clk)
q <= d;
endmodule
simulation: