review:
A memory is composed of a memory bank and MAR+MDR, and a memory bank is composed of a memory matrix composed of multiple memory cells.
Working principle: The memory matrix, decoder and control circuit are assembled together to form a memory chip, which has chip select lines, address lines and data lines, so as to understand how to address.
Specific classification: The previous chapter talked about the classification and composition of storage, which can be classified according to materials or functions: Cache, memory, and external storage.
The memory is also divided into RAM and ROM. RAM is a random storage register. The time required for reading has nothing to do with the storage location. It is divided into SRAM and DRAM. One of these two relies on flip-flops and the other relies on capacitors.
Because DRAM is a destructive reading and needs to be refreshed, it has more main memory and SRAM has more cache to solve the problem of inconsistent CPU and memory speed. Both of these data will be lost when the power is turned off.
So ROM was produced.
Instruction format
Instruction addressing mode
Two design methods: CISC and RISC
An instruction is a machine language. The software can work because it is first translated into instructions, and the hardware works under the command of the instructions.
An instruction is divided into operation code + address code
Assuming that the main memory stores not only instructions but also data, then the execution process of an instruction is like this
Suppose the execution is
Put the content of ( )+(
)
inside, the next instruction is A4
The address is 6 bits, and the content in the address is 32 bits. The content may be data or instructions. If it is an instruction, the operation code occupies 8 bits, and the 4 address codes occupies 6 bits.
Because the address code occupies 6 bits, there are 64 different positions in total. As described in the figure above, the main memory is accessed 4 times in this process.
If the storage data and the instruction are placed in two different places, then after executing an instruction, you can directly read the next instruction, that is, address +1, so a PC and a counter will be added. This is not necessary . The instruction structure can be optimized to a three-address instruction, and then optimized to a two-address instruction and a one-address instruction, as shown in the figure:
No matter how you change it, the instruction word length is not changed. This is called a fixed-length instruction word structure : the instruction length is fixed
There is also a variable-length instruction word structure : the instruction becomes shorter as the address code decreases. Such as: change from one address to zero address
Fixed length opcode and extended opcode
The extended operation code represents one of the states as an extended state, and then the following address code represents the operation code. The operation code is extended, the address is reduced, and it becomes an n-1 address instruction
Huffman coding
How to design extensible instructions ? Assuming the instruction word length is fixed to 16
Data storage
In fact, this part has also been mentioned before, big-endian mode: high-end mode: low-end mode: low-end mode.
Store by word, store by byte.
There are also aligned and unaligned
Misalignment is inefficient.
Instruction addressing
PC-based sequential addressing and jump addressing
Data addressing has different addressing modes
The formal address does not really correspond to the address in the memory, but according to the storage characteristics, it is converted into the real address in the memory
This is the one-address instruction, of course there are also two-address instructions
Address immediately
Direct addressing
Indirect addressing
How to judge the end of addressing?
Add a bit, if it is 1, it means that the storage is a formal address, if it is 0, it means that the storage is an actual address
Register addressing
Register indirect addressing
Implicit addressing
Put an operand in the hardware by default
to sum up
