homework 6
1. Multiple choice questions (19 questions in total, 57 points)
1. (Multiple choice, 3 points) The memory system of a computer refers to ______.
- A. RAM memory
- B. ROM memory
- c. Main memory
- D. cache, main memory and external memory 3 points
2. (Single-choice question, 3 points) Compared with the internal memory, the characteristic of the external memory is ______.
- A. Large capacity, fast speed and low cost
- B. Large capacity, slow speed, low cost
- C. Small capacity, fast speed, high cost
- D. Small capacity, fast speed, low cost
3. (Multiple choice, 3 points) The storage unit refers to ______.
- A. A storage element that stores a bit of binary information
- B. A set of all storage elements storing a machine word
- C. A collection of all storage elements that store a byte
- D. A collection of all storage elements that store two bytes
4. (Single-choice question, 3 points) The storage capacity of a memory chip is 8K×8 bits, then the sum of its address line and data line pins is ______.
- A. 12
- B. 13
- C. 21
- D. 22
5. (Single-choice question, 3 points) A computer has a word length of 64 bits and a memory capacity of 32MB. If it is addressed by halfword, then its address range is ______.
- A. 64M
- B. 32M
- C. 16M
- D.8M
6. (Multiple choice, 3 points) For a 256K×8 memory, the sum of its address lines and data lines is ______.
- A. 16
- B. 18
- C. 26
- D. 20
7. (Multiple choice, 3 points) The storage capacity of a certain memory chip is 8K×12 bits, so its address line is ____.
- A. 11
- B. 12
- C. 13
- D. 14
8. (Single-choice question, 3 points) A DRAM chip has a storage capacity of 512K×8 bits, and the number of address lines and data lines of the chip is ______.
- A. 8,512
- B. 512,8
- C. 18,8
- D. 19,8
9. (Single-choice question, 3 points) The initial boot program of a computer without external memory can be placed in ______.
- A. RAM
- B. ROM
- C. RAM and ROM
- D. CPU
10. (Multiple choice, 3 points) EPROM refers to ______.
- A. Read and write memory
- B. Read-only memory
- C. Programmable read-only memory
- D. Optically Erasable Programmable Read-Only Memory
11. (Single-choice question, 3 points) If the system program of a single-chip microcomputer is not allowed to be changed by the user during execution, ______ can be selected as the memory chip.
- A. SRAM
- B. Flash memory
- C. cache
- D. Secondary memory
12. (Single-choice question, 3 points) If one of the input values of the "NAND" gate is "0", then its output value is ______.
- A. is "0"
- B. is "1"
- C. Depends on other input values
13. (Single-choice question, 3 points) Assume that there is a parity bit in the following character codes, but there is no data error, and the character codes that use odd parity are ______. (The four numbers are ①10011010 ②11010000 ③11010111 ④10111100)
- A. ①③
- B. ①
- C. ②④
- D. ④
14. (Single-choice question, 3 points) The reason why the dual-port memory can read/write at high speed is because of the use of ______.
- A. New Devices
- B. Pipeline technology
- C. Two sets of independent read and write circuits
- D. High-speed chip
15. (Single-choice question, 3 points) A read/write conflict will occur in a dual-port memory under ______ conditions.
- A. The address codes of the left port and the right port are different
- B. The address codes of the left port and the right port are the same
- C. The data codes of the left port and the right port are different
- D. The data codes of the left port and the right port are the same
16. (Single-choice question, 3 points) There are 4 memory modules in the module 4 interleaved memory, and they have their own ______.
- A. Address Register
- B. Address Register and Instruction Register
- C. Address Register and Data Buffer Register
- D. Address register, data buffer register and instruction register
17. (Single-choice question, 3 points) A computer uses 4-bank interleaved memory, assuming that the main memory address (decimal) sequence that appears on the memory bus is 8005, 8006, 8007, 8008, 8001, 8002, 8003, 8004, 8000 , the address where the buffer conflict may occur is
- A. 8004,8008
- B. 8002,8007
- C. 8001,8008
- D. 8000,8004
18. (Multiple choice, 3 points) Interleaved memory is essentially a ______ memory that can _____ perform ______ independent read and write operations.
- A. Modular, parallel, multiple
- B. Modular serial, multiple
- C. monolithic, parallel, one
- D. Integral, serial, multiple
19. (Single-choice question, 3 points) For a computer system with a multi-bus structure, the ______ method is the most effective way to improve the throughput of the system.
- A. Multi-port memory
- B. Increase the speed of main memory
- C. Cross-addressing multi-block memory
- D. Cache memory
2. Fill in the blanks (11 questions in total, 43 points)
20. (Fill in the blank, 3 points) DRAM is refreshed by reading out. Because the MOS gate capacitance charge of the storage unit is restored during the readout process, and the contents of the original unit are kept, the readout process is a regeneration process. There are three commonly used refresh methods: ____, ____, and ____.
my answer:
3 points
(1) concentrated
(2) scattered
(3) asynchronous
21. (Fill in the blank, 3 points) ____ can provide high performance, low power consumption, high reliability and instant start-up capability, so it is used as a solid state disk in portable computers.
my answer:
(1) Flash memory
22. (Fill in the blank, 3 points) The performance indicators of memory are mainly ____, ____, access (storage) cycle and memory bandwidth.
my answer:
3 points
(1) Storage capacity
(2) Access time
23. (Fill in the blank, 3 points) Due to the limited capacity of the memory chip, it often needs to be expanded in ____ and ____ to meet the actual needs.
my answer:
3 points
(1 person
(2) words
24. (Fill in the blank, 3 points) The CPU can directly access ____ and ____, but cannot directly access disks and CDs.
my answer:
3 points
(1) Cache
(2) main memory
25. (Fill in the blank, 3 points) The refresh of the dynamic memory is carried out according to ____ (row/column); if the capacity of the memory cell is 64K, double decoding is adopted and the address lines are sent to two decoders on average. Then the number of bits of the refresh address counter is ____.
my answer:
3 points
(1) line
(2) 8
26. (Fill in the blank, 5 points) When the chip select signal is 101, select a 128K*8-bit memory chip, then the first address of the memory unit space where the chip is located is ____H, and the last address is ____H. (For the convenience of comparison, it is written as 5 digits )
my answer:
5 points
(1) A0000
(2) BFFFF
27. (Fill in the blank, 5 points) There is a 1024K×32-bit memory, which is composed of 128K×8-bit DRAM, and a total of ____ pieces of DRAM chips are needed. The organization method is a group of ____ pieces (bit extension), and a total of ____ group (word extension).
my answer:
5 points
(1) 32
(2) 4
(3) 8
28. (Fill in the blank, 5 points) For a 64K×8-bit DRAM, the number of rows and columns of the storage matrix is the same, the number of rows is ____, the row address lines need ____, and asynchronous refresh is adopted. If the unit refresh interval does not exceed 8ms, The refresh signal period is ____μs (that is, how often a row is refreshed).
my answer:
5 points
(1) 256
(2) 8
(3) 31.25
29. (Fill in the blank, 5 points) Quantitative analysis compares sequential and cross storage methods.
Suppose the memory capacity is 64MB, the word length is 64 bits, the number of modules is m=8, the storage cycle T=100ns, the data bus width is 64 bits, and the bus transfer cycle τ=50ns. If read 4 words continuously.
Sequential memory and interleaved memory read m=4 words continuously and the total amount of information is ____bit.
The time required to continuously read 4 words from the sequential memory is ____ns, and the bandwidth is ____bps.
The time required to continuously read 4 words from the interleaved memory is ____ns, and the bandwidth is ____bps.
my answer:
5 points
(1) 256
(2) 400
(3) 640M
(4) 250
(5) 1024M
30. (Fill in the blanks, 5 points) If the word length of the memory is 64 bits, the number of modules m = 8, organized in a crossover manner, the
storage period T = 200ns, the data bus width is 64 bits, and the bus transmission period τ = 50ns.
Then the amount of information for continuously reading m=8 words is ____ bits,
the time required to continuously read 8 words is: ____ns,
the bandwidth of the interleaved memory is: ____bps (for the convenience of comparison, nM, n is rounded to integer)
my answer:
5 points
(1) 512
(2) 550
(3) 931M