IIC communication protocol
I2C (IIC, Inter-Integrated Circuit), a serial bus composed of data line SDA (data) and clock SCL (clock), bidirectional transmission.
The high-speed IIC bus can generally reach more than 400kbps.
IIC is a half-duplex communication method.
Timing diagram
Host: start signal——->first position——>second position——> …….. ——–>eighth position——>waiting for response signal——->stop signal
A rough data transmission process is : the host sends a start signal to the SDA line, indicating that there is a signal to transmit. At this time, all the chips connected to the IIC bus are in the receiving state. Next, the host sends the data it wants to communicate with it. The transmitted slave address signal, all slaves will receive the address signal and match with their own inherent address signal. When the pairing is successful, the data transmission will be carried out under the drive of the clock signal. The data transmission is according to Data is transferred in units of 8 bits. In the transmission process of each bit, during the high level of SCL, the stability of the SDA value must be ensured, otherwise an error will occur, and the change of the SDA value occurs during the low level of SCL. Finally, all 8 bits are transmitted, and the slave generates a response signal to the host. After receiving the response signal, the host decides whether to send a new set of data or terminate the transmission.
Timing Analysis
idle state
When SDA and SCL are high at the same time, the bus is idle
start signal and stop signal
Start signal: When SCL is high, SDA level transitions from high to low
Stop signal: When SCL is high, SDA transitions from low to high
response signal
Each time the transmitter sends a byte (8 pulses), the bus is released between the ninth pulses, and the receiver returns an ACK signal. The protocol stipulates that a low level is a valid response, and a high level is an invalid response.
data validity
When the clock signal is at a high level, the data must remain stable, and when the clock signal is at a low level, the level on the data line is allowed to change.
That is, the data must be ready before the clock signal arrives and remain after the falling edge of the clock signal.
data transmission
I2C is a synchronous transmission, the clock controls the transmission of data bits, and is edge-triggered.