The advantage of DMA is that it does not require CPU intervention during data transmission, which can greatly improve the efficiency of the CPU.
DMA is very important in large-capacity data transmission, such as image data transmission, SD card data transmission, USB data transmission and so on.
S3C2410 has four DMAs. Each DMA supports basically the same working mode, but the supported source Dest may be slightly different.
So how to use DMA, S3C2410 integrates DMA controller inside, we only need to configure the register to realize DMA transmission.
Steps and points:
1. Where does the data come from and where does it go?
To use DMA, of course, we must first know the direction of data flow. The DISRCx register is the source address of the data stored in the DMA initial source register. DIDSTx is the initial destination register of DMA, which should store the destination address of the data.
2. What bus does the data go on? Is the address fixed?
We also need to know what bus the source and destination data storage devices are on (AHB system bus, generally high-speed such as memory, APB peripheral bus low-speed, such as SD, UART);
And after the end of the data transmission, the starting address is restored to the starting address before sending, or the current end +1 is used as the new starting address.
These settings are configured in the DISRCCx and DIDSTCx registers.
3. How is the data transmitted? What equipment is the source and destination? Do you want to reload automatically?
It is necessary to determine whether the data transmission method is request or handshake (handshaking is recommended). According to the above bus, determine which clock is synchronized with (HCLK, PCLK), unit transmission or burst transmission, byte transmission or word transmission, and whether it is heavy Load. Is it a single service (send only once) or multiple services (send continuously in a loop), and the size of the data transfer.
Select the source and destination devices, here the DMA controller supports:
Ch0:nXDREQ0,UART0,SDI,Timer,USB EP1
Ch1: nXDREQ1,UART1,I2SSDI,SPI0,USB EP2
Ch2:I2SSDO,I2SSDI,SDI,Timer, USB EP3
Ch3: UART1, SDI, SPI1, Timer, USB EP4
Finally, determine whether the interruption occurred at the end of the transmission (whether the CURR_TC count is 0).
These are all set in DCONx.
4. How to start DMA transfer and stop DMA, these are set in DMASKTRIG.
DMA has 3 transfer modes:
S3C2410 DMA is introduced because it is so important to performance! Only by using DMA can the performance of the CPU go up! S3C2410 has four DMAs. Each DMA supports basically the same working mode, but the supported source Dest may be slightly different. See the Datasheet for details.
Here the specific DMA CONTROL register (DCON) configuration description, and then lead to various working modes of DMA.
- Atomic transfer: Refers to a single atomic operation of DMA. It can be in Unit mode (transmitting 1 data size) or burst mode (transmitting 4 data sizes), which corresponds to DCON[28].
- Data Size: Refers to the data bit width of a single atomic operation, 8, 16, 32, corresponding to DCON[21:20].
- Request Source: There are two sources of DMA request, software & hardware modules, controlled by DCON[23]; when it is the former, the software sets bit 0 of the DMASKTRIG register to trigger a DMA operation. When it is the latter, the specific source is controlled by DCON[26:24], and different hardware modules trigger a DMA operation at a certain time, depending on the different hardware modules.
- DMA service mode: There are two working modes of DMA, single service mode & overall service mode. In the previous mode, a DMA request completes an atomic operation, and the value of transfer count is reduced by 1. In the latter mode, a DMA request completes a batch of atomic operations until the transfer count is equal to 0, which means that an overall service is completed. Specifically corresponding to DCON[27].
- RELOAD: In reload mode, when the value of transfer count becomes zero, the values of src, dst, and TC will be automatically added to CURR_DST, CURR_SRC, and CURR_TC, and a new DMA transfer will be started. This mode is generally used together with the overall service mode, which means that when an overall service starts, the values of src, dst, and TC have been loaded, so it can be changed to the address of the next service. The following statement is recommended in the 2410 description document To judge the start of the current service, the values of src, dst, and TC can be changed: while((rDSTATn & 0xfffff) == 0);
- Req&Ack: There are two protocols for DMA request and response, Demard mode and Handshake mode. The two have different timing definitions for Request and Ack: In Demard mode, if the DMA completes a request, if the Request is still valid, then the DMA considers this to be the next DMA request; in Handshake mode, the DMA waits after completing a request The Request signal is invalid, and then the ACK is also invalid, and then wait for the next Request. This may be used when designing external DMA requests.
Total transfer length: The total length of a DMA overall service transfer is:
Data Size × Atomic transfer size × TC (bytes).
S3C2410's DMA supports four types of DMA transfer:
- System bus to system bus (ASB/AHB to ASB/AHB)
- System bus to peripheral bus (ASB/AHB to APB)
- Peripheral bus to system bus (APB to ASB/AHB)
- Peripheral bus to peripheral bus (APB to APB).
S3C2410 has four DMA channels in total, each with 5 request sources.
- Ch0:nXDREQ0,UART0,SDI,Timer,USB EP1
- Ch1: nXDREQ1,UART1,I2SSDI,SPI0,USB EP2
- Ch2:I2SSDO,I2SSDI,SDI,Timer, USB EP3
- Ch3: UART1, SDI, SPI1, Timer, USB EP4
S3C2410 DMA 三个比较重要的信号，引用2410官方文档：
- DMA REQ: In the Single service mode, these three states of main FSM are performed and then stops, and waits for another DMA REQ. And if DMA REQ comes in, all three states are repeated.
- DMA ACK: DMA ACK is asserted and then deasserted for each atomic transfer. In contrast, in the Whole service mode, main FSM waits at state-3 until CURR_TC becomes 0. Therefore, DMA ACK is asserted during all the transfers and then deasserted when TC reaches 0.
- INT REQ: INT REQ is asserted only if CURR_TC becomes 0 regardless of the service mode (Single service mode or Whole service mode).
S3C2410 DMA状态机：
S3C2410 的DMA使用一个具有三个状态的有限状态机进行DMA 传输的流程控制，引用2410官方文档：
- State-1. As an initial state, the DMA waits for a DMA request. If it comes, it goes to state-2. At this state, DMA ACK and INT REQ are 0.
- State-2. In this state, DMA ACK becomes 1 and the counter (CURR_TC) is loaded from DCON[19:0] register. Note that the DMA ACK remains 1 until it is cleared later.
- State-3. In this state, sub-FSM handling the atomic operation of DMA is initiated. The sub-FSM reads the data from the source address and then writes it to destination address. In this operation, data size and transfer size(single or burst) are considered.
每当一次DMA操作结束，不管是使用什么服务模式，DMA状态机都会自动地从状态三回到状态一，开始另一次操作。注意这里信号是DMA REQ 和 DMA ACK，而最终引脚信号是nXDREQ 和 nXDACK，所以最后实际输出的电平与这里的描述是相反的。
S3C2410 DMA 的服务模式：
共有两种服务模式，一种是单一服务模式（single service），另外一种是整体服务模式（whole service）。
在单一服务模式下，不使用传统的DMA计数器，三个DMA状态被顺序执行一次后停止，等待DMA 请求再一次来临后再重新开始另一次循环。
在整体服务模式下，使用传统的DMA 计数器，状态机会停留在状态三，直到DMA计数器的值减为零，再回到状态一，等待下一次DMA请求。
S3C2410 DMA 数据传输模式：
共有两种数据传输模式：
- 单位数据传输模式：执行一次读操作和一次写操作。
- 并发数据传输模式：执行四次读操作和四次写操作。
S3C2410 DMA 的基本时序：
nXDREQ请求生效并经过2CLK周期同步后，nXDACK响应并开始生效，但至少还要经过3CLK的周期延迟，DMA控制器才可获得总线的控制权，并开始数据传输。 
S3C2410 DMA 的两种协议模式： 
- 请求模式：If XnXDREQ remains asserted, the next transfer starts immediately. Otherwise it waits for XnXDREQ to be asserted.
- 握手模式：If XnXDREQ is deasserted, DMA deasserts XnXDACK in 2cycles. Otherwise it waits until XnXDREQ is deasserted.
S3C2410 DMA REQ与ACK 协议类型：
共有三种协议类型：
- 单一服务请求：
- 单一服务握手：
- 整体服务握手：
根据上面所说的服务模式和协议模式，很容易推知这三种协议的时序分别是什么。