learning target:
1, understand the concepts and features nor flash memory chips
2, using the master chip s3c2440 plug nor flash erase operation to read and write
1, NOR Flash's brief
NOR Flash was originally developed by Intel Corporation in 1988 out, is one of two major non-volatile memory on the market today, it's completely changed the appearance on the market by the memory EPROM (Erasable Programmable Read-Only-Memory electricity programmable read only memory) and EEPROM (electrically erasable read only memory electrically erasable programmable Read - Only memory) domination. NOR Flash biggest characteristic supports XIP (Execute On Chip), the program may be executed either directly within the NOR flash chip, no need to relocate the code copied into the RAM of NOR Flash runtime. The NOR Flash separate address and data lines, read data, and a RAM is very similar, can be provided as long as the address data, data bus data will be able to give correct. However, it can not be directly write operation is performed to send the command sequence needed fixed before the write operation, and then sends the write address and data operations.
The minimum access unit NOR Flash memory is generally divided into 8-bit and 16-bit, there are some NOR Flash device supports both 8-bit and 16-bit mode, the bit width of the Flash in the design of the hardware can be selected, when the chip lead BYTE # contact pin is high, the chip operating at 16 bits wide mode, BYTE # pin is set low, the bit width of the chip to work in 8-bit mode.
Usually a plurality of sectors NOR Flash, NOR Flash sector is the smallest unit of erase, Nor Flash size of each sector is not fixed, the sector is generally divided into two modes of emission Top Boot part and Bottom Boot part. The difference between these two forms is different in small sectors of NOR Flash chip is placed in position, Bottom the Boot tile type NOR Flash chip address is the address 0, and Top Boot part type NOR Flash addresses in the chip pieces high address.
2, NOR Flash pin presentation (to MX29LV60DBTI chip, for example)
MX29LV60DBTI 16M-BIT is a NOR Flash chip, which pin as shown below:
Pin Description table
| symbol | Pin name | Features |
| A0-A19 | Address input | Address signal, address information indicating the data to be read |
| Q0 ~ Q15 | Data input / output | Data input / output pins, the output data read cycle, a write cycle the input data |
| THIS# | Chip Enable | CE # is low, the chip is selected, the operation performed before a subsequent valid |
| WE# | Write Enable | With CE # and OE # and the address pins and data pins used together, when CE # low, a high level OE #, WE # is low, Q0 ~ Q15 data is written into A0 ~ A19 denotes address |
| BYTE# | Word or byte selection input | When it is high, the data output mode for the 16bit; low, the data output mode of 8bit |
| RESET# | Hardware reset / unlock pin Sector Protection | Hardware reset pin, when the input signal is low, the chip is reset |
| OE# | Output Enable | With CE # and WE # and the address pins and data pins used together, when CE # low, the high level WE #, OE # is low, the data transfer memory addresses A0 ~ A19 to Q0 ~ on the A15 |
| RY/BY# | RY / BY # output pin | Ready and Busy signal for outputting, when actually used may not take, can be used instead of the command to query the status of NOR Flash |
| VCC | The power supply pins (2.7v ~ 3.6v) | Chip power supply |
| GND | Jibikiashi | The chip power |
| WP#/ACC | Hardware write protection / acceleration pins | Hardware write protection pin, active low |
| NC | Not connected to the internal pin | Do not connect |
3, NOR Flash S3C2440 connected in FIG.
NOR Flash data width is 16 bits, when the connection is connected to address lines 2440 must be offset processor. s3c2440 vacant address lines A0, A1 are connected NOR Flash address lines A0, A2 connected NOR Flash address lines A1, sequentially ordered. Connection is reason to misalignment: 2440 each address corresponds to a processor BYTE data unit, and each address is 16-BIT NOR FLASH is a corresponding HALF-WORD (16-BIT) data units. In order to maintain the matching, it is necessary to offset connector. Thus, from the lowest address A0 bit signal is sent out to the 2440 processor 16-BIT FLASH it was shut off.
The above described process is too abstract, the following reasons offset by drawing to explain the connection:
①, ARM processor needs to read the address from a 0x0 BYTE
- 0x0 ARM processor sends signals on address lines An-A0;
- Since 2440, the address A1 is connected NOR Flash A0,16-BIT FLASH address signals on its own An-A0 seen that 0x0, 0x0 and the cell output corresponding to the address data to the 16-BIT D15-D0;
- ARM processor knows that the access of 16-BIT FLASH, reads desired data from a BYTE D7-D0.
②, ARM processor requires a BYTE read from address 0x1
- 0x1 ARM processor sends signals on address lines An-A0;
- Since 2440, the address A1 is connected NOR Flash A0,16-BIT FLASH address signals on its own An-A0 still see 0x0, 0x0 and the cell output corresponding to the address data to the 16-BIT D15-D0;
- ARM processor knows that the access of 16-BIT FLASH, reads desired data from a BYTE D15-D8.
Note: Some ARM processor can set the internal displacement address. Support software for the processor to select an address offset, when the connection 16-BIT FLASH does not need address lines to misalignment hardware. In the design, the chip should refer to the data sheet, the manual is correct, to avoid unnecessary trouble (such as stm32 connection is A0 ~ A0).
4, S3C2440 NOR Flash drive timing configuration
s2c2440 NOR Flash memory controller then read timing diagram
Pictured s3c2440 NOR Flash read timing of the operation, Tacs represents a chip enable setup time before the address signals (address signals both need to set how long, in order to enable chip select signals), Tcos represents the OE # signal enables the chip select ago set time energy, Tacc access cycle represents the data, Tcoh OE # signal indicates the holding time after the release of the chip select signal, Tcah indicates holding time after the release of the chip select signal is an address signal. Since s3c2440 general purpose processor performance, he may access different external company generated different models of NOR Flash, so these parameter values to be set according to a timing chart of the connected model of NOR Flash.
The following parameters according to the above-described configuration MX29LV60DBTI NOR Flash chip timing diagram, a timing chart shown in FIG MX29LV60DBTI follows:
NOR Flash chip internal timing chart showing a read operation MX29LV60DBTI
MX29LV60DBTI NOR Flash chip timing chart showing specific values of the parameters
Tce: chip select signal output enable long data is valid, the maximum value is 70ns
Toe: read signal sent long after the output data is valid, the maximum value is 30ns
Taa: the address data valid signal is issued, the maximum value is 70ns
Trc: Read cycle time, minimum 70ns
Tdf: When OE # CE # or higher, a data pin floating time, the maximum 30ns (negligible provided, when the end data is read, a new read signal is issued, to over 70ns, the data line data is valid, this pin floating time has no effect)
Represents the maximum value after sending the signal, after the maximum time interval, the data signal pins must be effective, within this range, it may be effective to pin the data signal.
For simplicity, we generally set 2440 CE #, OE #, ADD simultaneously control signal, read data after the data retention pin 70ns. NOR Flash s3c2440 connected Bank0 address, configuration timing registers BANKCON0, each bit of the register shown in the following figure:
The memory controller clock signal is provided by a clock signal HCLK, HCLK is assumed that the set value of 100M, 1clock = 10ns. According to the foregoing analysis, Tacs, Tcos register bit is set to 0, Tacc register is set to 101 = 8clocks.
5, NOR Flash read operation
NOR Flash memory is a class similar to the interface, and read as memory read, the address of the corresponding transmission directly to obtain the corresponding data will be able to
unsigned int nor_read_word(unsigned int base, unsigned int offset)
{
volatile unsigned short *p = (volatile unsigned short *)(base + offset);
return *p;
}
unsigned int nor_dat(unsigned int offset)
{
return nor_read_word(NOR_FLASH_BASE, offset);
}
6, NOR Flash sector erase
NOR Flash erase sector, should send the appropriate command, transmits the command sequence is as follows:
The first bus cycle: 555 to write the address AA
The second bus cycle: write address 55 to the 2AA
The third bus cycle: write address 80 to 555
The first four bus cycles: the write address 555 to the AA
Fifth bus cycle: To 2AA address written 55
Sixth bus cycle: to write the sector 30 to be erased
nor_write_word void (Base unsigned int, unsigned int offset, unsigned int Val)
{
volatile unsigned * P = Short (Short volatile unsigned *) (Base + offset);
* P = Val;
}
/ * offset angle is based cpu see * /
void nor_cmd (offset unsigned int, unsigned int cmd)
{
nor_write_word (NOR_FLASH_BASE, offset, cmd);
}
/ * wait programming is done: read data, when the end of Q6 represents no change * /
void wait_ready (unsigned int addr)
{
int Val unsigned;
unsigned int pre;
pre = nor_dat (addr);
Val = nor_dat (addr);
the while (! (& Val (<<. 1. 6)) = (pre & (<<. 1. 6)))
{
pre = Val;
Val = nor_dat (addr);
}
}
erase_nor_flash_sector void (unsigned int addr)
{
the printf ( "Erasing ... \ n-\ R & lt");
nor_cmd (0x555 <<. 1, 0xAA); / * unlock * /
nor_cmd (0x2aa <<. 1, 0x55);
nor_cmd (0x555 . 1 <<, 0x80); / * * a sECTOR ERASE /
nor_cmd (0x555 <<. 1, 0xAA); / * unlock * /
nor_cmd (0x2aa <<. 1, 0x55);
nor_cmd (addr, 0x30); / * sector issued address * /
wait_ready (addr); / * wait until the operation * /
}
CPU external NOR Flash, NOR Flash is actually the address mapping for the unified addressing CPU. Since the offset nor_cmd function is based on the CPU address of the angle to see, and the address on the chip NOR Flash manual write command from the actual physical address of NOR Flash, NOR Flash is 16 bits, which should correspond to address 0 of the CPU address 0 and 1 address. Therefore, NOR Flash physical address from the CPU's point of view, the address value should be twice NOR Flash point of view, so when writing to an address, to the point of view of NOR Flash address right one .
7, NOR Flash write operation
When data is written to the address in NOR Flash, also should send the appropriate command, transmits the command sequence is as follows:
The first bus cycle: 555 to write the address AA
The second bus cycle: write address 55 to the 2AA
The third bus cycle: write address A0 to 555
A fourth bus cycle: To write data to the destination address
write_nor_flash void (unsigned int addr, unsigned int Val)
{
/ * programming * /
nor_cmd (0x555 <<. 1, 0xAA); / * unlock * /
nor_cmd (0x2aa <<. 1, 0x55);
nor_cmd (0x555 <<. 1, 0xA0); / * Program * /
nor_cmd (addr, Val);
/ * wait programming is done: read data, when the end of Q6 represents no change * /
wait_ready (addr);
}
It is noteworthy that the write operation is only written to address the content of the target is 0xff, data can be written to the right, therefore, NOR Flash to the sector erase operation when writing in general. NOR Flash only when data is written to the address by 1 to 0, can not by from 0 to 1.
NOR Flash assumed that an address stored in the character a (0x61), if not erased before the write word G (0x47) to the address, the last address is the content of A (0x41). For the following reasons:
Character into a binary ---> 1100001
G character into a binary ---> 1000111
Since the write data bits can only be from 0 to 1, the final result 100001, corresponding to the raw data and performs new data writing operation &
Performing the above steps to NOR Flash, the above-described verification process
①, a character is written to address 0x80000
②, does not erase the character G 0x80000 sector write address, then the address in the read data, read the actual contents 0x41, 0x47 is not, in line with the results described above.
