Suddenly found a very good course, there are the DMA, very good, spent 69 buy it, DMA link as follows:
https://time.geekbang.org/column/article/118657
note:
Personal sort, no responsibility is wrong.
0. CPU control data transmission Introduction
Data transmission control by the CPU, there are two: query, interrupts.
0.1 query
Query is controlled by a program, if the program executing on the CPU required for data transmission, CPU peripheral status inquiry, if the peripheral is ready, then the data transfer.
0.2 interrupt
When a peripheral needs to exchange data with the CPU, peripheral asserts an interrupt request to the CPU, the CPU interrupt the current program execution, the data transfer request corresponding to the peripheral. After the end of the data transfer peripherals, CPU continues the interrupted program.
The above two methods, the data are required to pass through the CPU, DMA data transfer described below control.
1. DMA Introduction
DMA mode, Direct Memory Access, also referred to as a set of data transfer mode, sometimes referred to as direct memory operation. DMA mode during data transfer, there is no saving the site, site restoration work and the like.
Since the CPU does not participate in the transfer operation, thus eliminating the need for CPU instruction fetch, fetch, and so the number of pumping operation. Modifying the memory address, transfer count the number of words, etc., it is not implemented by software, but hardware implementation direct line. We can meet the requirements of high-speed DMA mode I / O devices, the CPU is also conducive to efficient play. (Reference from Baidu)
2. Works
Direct memory access (DMA) is used to provide high speed data transfer between peripherals and memory or between a memory and a memory. Without CPU intervention, data can be moved by DMA quickly, which saves CPU resources to do other operations.
If the device requires a data transfer, the device directly transmits the first memory through a bus DMA request (DMA bus takeover) by DMA to the CPU, CPU request signal is received, after the end of the current clock cycle, in accordance with the priority CPU will signal DMA and the order requested by the respective DMA request. After the CPU request corresponding DAM, make the control of the bus, the control bus to allow DMA. Under the management of DMA, memory, and peripherals exchange data directly, without CPU intervention, after the end of the data transfer, the DMA control of the bus to the CPU.
3. DMA transfer characteristic
(From Baidu Encyclopedia)
DMA is an important feature of all modern computers, it allows hardware devices of different speeds to communicate without the need to depend on a lot of CPU interrupt load. Otherwise, CPU need to copy from the source of each segment to register, and then put them back again to write new place. At this time, CPU for other tasks, it can not be used.
DMA transfer to a memory area is copied from one device to another, the CPU initializes the transfer operation, the operation itself is transmitted to the implementation and completion by the DMA controller. A typical example is a mobile external memory block to go faster memory chip. Like such an operation does not allow the processor to work delays, but can be re-scheduled to deal with other work. DMA transfer algorithm for high-performance embedded systems and networks is important.
For example, the ISA DMA controller PC 8 has DMA channels, wherein the channels 7 let the PC's CPU is utilized. Each DMA channel has a 16 yuan address register and a count register 16 yuan. To initialize the data transmission, with the driver address setting means and the count register DMA channel, and the direction of data transfers, read or write. Then instructs the transmission operation starts DMA hardware. When the end of the transmission, the device will be notified by way of interrupts CPU.
However, DMA transfer mode only lighten the burden on the CPU; a system bus is still occupied. Especially when transferring large files, CPU usage may be less than 10%, but the user will feel when the system is running part of the program becomes quite slow. The main reason is to run these applications (especially some large software), the operating system also requires a large amount of data transmitted from the system bus; it caused long waiting time.
4. Basic Operation
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Peripheral transmit DMA request to the DMAC by the CPU
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DMA requests corresponding CPU, DMA gains control of the bus
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The memory address transmitted by the DMAC, and determines the length of the transmission data block.
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Perform DMA transfer.
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DMA operation is completed, the control of the bus is returned to CPU.
The bus control right to
When DMA control bus for data transfer, the CPU is not occupied by the bus, at this time if other programs require CPU peripheral or do some other things how to do? This involves the question of the right to use the bus.
5.1 Stop CPU access memory
When requesting a DMA peripheral control section of the transmission data, the CPU relinquishes control of the bus until the transmission complete set of data, then the CPU takes over the bus.
Advantages: simple control
Cons: DMA memory access stage, the wasted memory cycles, memory, because the memory cycle time is generally less than two IO data transmitting device spacing.
5.2 cycle steal
(From Baidu Encyclopedia)
When the I / O device DMA requests is not, the CPU requires access memory according to the procedure; Once I / O device has a DMA request by I / O devices or diversion of a few memory cycles.
Two cases may be encountered I / O device DMA transfer requirements:
The inner (1) and the CPU does not require access, such as the CPU is executing a multiply instruction. Since a long multiply instruction execution time, then the I / O access does not conflict with the access CPU, i.e., I / O devices diversion twelve memory cycles no effect on the CPU executes the program.
(2) I / O device within the access requirements also requires the CPU to visit, the visit This creates a conflict, the priority I / O device access in this case, because the time required I / O access, prior to a I / O data in the next access must complete before the arrival of the access request. Obviously, in this case I / O device diversion twelve memory cycles, means that the CPU delays the execution of instructions, or, more specifically, during instruction execution in the CPU access is inserted into a DMA request, a misappropriated two memory cycles.
Compared with the method of stopping the CPU DMA access and cycle stealing methods to achieve both an I / O transfer, and played a better efficiency of the CPU and memory, is a widely used method. However, I / O devices each have a cycle steal request control of the bus, to establish process control of the bus and return control of the bus, it transmits a memory word to be occupied for a period, but the DMA controller is generally 2-5 memory cycles (depending on the delay logic may be). Thus, the method is applicable to the case of cycle stealing I / O devices to read and write cycle period is greater than the storage memory.
5.3 the DMA access and the CPU are alternately
If the working cycle of the CPU is longer than the memory access cycle number, then the method may alternately access the CPU and the DMA transfer enable simultaneously achieve maximum efficiency. Suppose the duty cycle of 1.2 [mu CPU, memory access cycle is less than 0.6μs, then a CPU cycle can be divided into two sub-cycles C1 and C2, wherein C1 visit for the DMA controller, the CPU C2 specifically for access.
In this manner not need to apply the right to use the bus, and to establish the return process, the right to use the bus is performed by time sharing C1 and C2. CPU and the DMA controller each have their own access to the address register, data registers and the read / write control register signal and the like. In the period C1, if the DMA controller has access requests, address, data signals may be sent on the bus. In the C2 cycle, such as the CPU has access request, and transfers the address and data signals. In fact, for the bus, which is C1, C2 to control a multiplexer, this shift control of the bus require little time, so the DMA transfer is very high in terms of efficiency.
6. Working Process
DMA operation process consists of three steps: the pre-processing stage, the data transfer, the transfer process.
6.1 pre-processing stage
Test device state; fed to the address register of the DMA controller device number, and the initiator; to be switched into the main memory starting address data to the main memory address counter; exchange data to be sent to the word counter number. When ready to send data to the external device (input) or the last received data has been processed (output), the DMA controller notifies the DMA request is issued, the application main memory bus.
6.2 data transfer
DMA data transfer may be a single byte (or word) as the basic unit for transmission (e.g., silver plate) in units of blocks, the data input and output operation of the DMA bus occupation is achieved by the circulation. Special need that this cycle is implemented by the DMA controller (not by the CPU executing a program), i.e., the data transfer phase is completed by the DMA (hardware) control.
6.4 treatment
DMA controller sends an interrupt request to CPU, CPU to execute the interrupt service routine to do DMA end of treatment, including whether the test data into the main memory is correct, the test for errors during transmission (an error into the diagnostic procedures) and decide whether to continue using DMA transmitting other data blocks and the like.
7. Why DMA transfer speed
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