S3C2440 integrates rich peripheral controllers (LCD controller, USB Device controller, USB Host controller, NAND FLASH controller, I2C controller, SPI controller, etc.). To control these peripherals, it is necessary to set the registers of the corresponding controller to generate the corresponding drive timing . Learning S3C2440, mainly how to configure registers. The following is the S3C2440 special function register address:
#define rBANKCON0 (*(volatileunsigned *)0x48000004) //Boot ROM control #define rBANKCON1 (*(volatileunsigned *)0x48000008) //BANK1 control #define rBANKCON2 (*(volatileunsigned *)0x4800000c) //BANK2 cControl #define rBANKCON0 (*(volatileunsigned *)0x48000004) //Boot ROM control #define rBANKCON1 (*(volatileunsigned *)0x48000008) //BANK1 control #define rBANKCON2 (*(volatileunsigned *)0x4800000c) //BANK2 cControl
Figure 1 Memory map
The following is a detailed analysis.
Figure 2 S3C2440 structural block diagram
First introduce AMBA (Advanced Micro-Controller Bus Architecture) is the On-Chip Bus on-chip bus specification introduced by ARM Limited, which is the mainstream standard of the chip bus at present. At the beginning, AMBA 1.0 only had ASB and APB. In order to save area, the bus protocol at this time used 3-state bus. In the later version of AMBA 2.0, AHB bus was added, and three groups of buses were defined: high-performance bus ( AdvancedHigh Performance Bus, AHB), system bus (AdvancedSystem Bus, ASB) and peripheral bus (Advanced PeripheralBus, APB).
Figure 3 Typical AMBA bus-based system
More information about AMBA bus can be viewed online, and there are a lot of Chinese information. It can be seen from Figure 2 that the LCD controller, interrupt controller, USB Host controller, power management, NAND controller, Camera controller, memory controller, AHB to APB bridge and DMA controller are mounted on the AHB bus . UART controller, I2C controller, USB Device controller, I3S controller SDI/MMC controller, GPIO, Watchdog/timer, RTC, ADC, SPI, AC97 are mounted on the APB bus . The following passage is taken from the S3C2440 chip manual:
"The S3C2440A holds 13 bus masters. They include DRAMrefresh controller, LCD_DMA, CAMIF DMA, DMA0,DMA1, DMA2, DMA3, USB_HOST_DMA,EXT_BUS_MASTER, Test interface controller (TIC) and ARM920T."
The S3C2440A has 13 master devices. When the master device on the AHB bus reads and writes the slave device, the sent address passes through the decoder of the AHB bus (through the memory mapping table) to generate the selection signal of the slave device corresponding to the address, and the slave device is selected; in this way, the slave device can be selected. Read and write.
Figure 4 AHB decoder
Figure 5 The specific implementation code of the decoder
The memory mapping table of the decoder is relatively independent. If the slave device on the AHB bus changes, the memory map must be modified to ensure that each address corresponds to the correct slave device. Below is an example of a memory map table.
Figure 6 Memory mapping table
Two kinds of memory maps are used: the memory map under normal operation and the memory map at restart. During normal operation, the slave devices of the microprocessor include internal RAM, external RAM, external ROM and AHB/APB bridge; when the system is restarted, the memory map of the system does not include the internal RAM, but 0x0000-0000 to 0x0000- The memory address segment of 03FF is mapped to nash. This section contains the startup and initialization code for the system. When the system starts and completes the initialization, the AMBA bus will generate a Remap signal and send it to the decoder to change the current memory mapping table of the decoder to the memory mapping table under normal working conditions.
The following is the address mapping of S3C2440
AHB Memory Map
Memory control 0x48000000 0x48000030
USB HOST 0x49000000 0x49000058
INTERRUPT 0x4a000000 0x4a00001c
DMA 0x4b000000 0x4b0000e0
CLOCK & POWER MANAGEMENT 0x4c000000 0x4c000018
*LCD CONTROLLER 0x4d000000 0x4d000060 0x4d000400(Palettestart address)
Nand Flash 0x4E000000 0x4E00003C
Camera Interface 0x4F000000 0x4F0000A0
APB Memory Map
UART0 0x50000000 0x50000028
UART1 0x50004000 0x50004028
UART2 0x50008000 0x50008028
PWM TIMER 0x51000000 0x51000040
USB DEVICE 0x52000140 0x5200026c
WATCH DOG TIMER 0x53000000 0x53000008
IIC 0x54000000 0x54000010
IIS 0x55000000 0x55000010
AC97 0x5b000000 0x5b00001C
I/O PORT
A 0x560000000x56000004
B 0x560000040x56000018
C 0x560000200x56000028
D 0x560000300x56000038
E 0x560000400x56000048
F 0x560000500x56000058
G 0x560000600x56000068
H 0x560000700x56000078
J 0x560000d0 0x560000d8
other 0x56000080 0x560000cc
RTC 0x57000040 0x57000088
ADC 0x58000000 0x58000014
SPI 0x59000000 0x59000034
SD Interface 0x5a0000000x5a000040
Summary: The decoder on the AHB bus generates the corresponding chip select signal according to the address, and selects the corresponding device. There is an AHB to APB bridge on the AHB bus. The bridge is the slave device of the AHB bus and the only master device on the APB bus. The bridge is a protocol converter (conversion from AHB protocol to APB protocol), and it also completes the address decoding of the APB bus.