Twelve, S3C2440 bare metal - SDRAM

12.1 SDRAM introduced

12.1.1 SDRAM definitions

SDRAM (Synchronous Dynamic Random Access Memory): synchronous dynamic random access memory - Memory
- Memory means work synchronizing clock needs to be synchronized, transmitting the transmission data are internal commands to it as a reference;
- Refers to dynamic memory arrays need to constantly refresh to ensure that data is not lost; comparison: SRAM (static - trigger)
- Refers to a linear random data is not stored sequentially, but the freedom to read and write the specified address compare data: Flash (block)
DDR: DDR is DDR SDRAM, SDRAM is an upgraded version. (DDR: double data rate, twice the rate SDRAM)
SDRAM gone through several generations: SDR DDR1 DDR2 DDR3 DDR4 - faster and faster (the name taken by the read and write rates)

12.1.2 SDRAM works

Select the first piece SDRAM, and then select the Bank, the final form of the same principles and retrieve data in reading and writing, first specify a row (Row), and then specify a column (Column), you can find the cells needed to accurately, this the basic principle is that the memory chip addressing, configuration diagram of the SDRAM (HY57V561620 (L) T)
- 4Mbit * 4banks * 16 ----> 32Mbyte ----> 2 ^ 5 * 2 ^ 20 requires 25 address lines (multiplexed address lines)
CPU issues chip select signal nSCS0 (with the same pin nGCS6) active, select SDRAM chips
SDRAM has four L-BANK, requires two address signals to select one, i.e. BA0, BA1.
Of selected chips in the same row / column (memory cell) addressed,
After locating the storage unit, the selected device will be unified data transmission.

12.2 memory address space

12.2.1 Address Space Layout (Memory MAP)

S3C2440 as 32-bit CPU, the address range can theoretically reach 4GB. 1GB removed address space for peripheral connection, there is a portion of the internal address of the CPU registers, the remaining address space is not used.
BANK0-BANK7 0x00000000-0x40000000
S3C2440 internal peripheral registers are in the address range 0x48000000-0x5FFFFFFF (GPIO-0x56000000)
SDRAM start address: 0x30000000
BANK expansion bus for connecting external peripherals, its address and an internal address in the peripheral linear address space.

12.2.2 addresses the relationship between memory and peripherals

12.2.2.1 memory controller features

Support little endian, big-endian (selected by software);
Each BANK address space is 128MB, a total of 1GB (8BANKs);
Programmable bus width (8/16/32-bit), but only select BANK0 two widths (16/32-bit);
A total of 8 BANK, BANK0 ~ BANK5 can support an external ROM, SRAM and the like, BANK6 ~ BANK7 other supports ROM, external SRAM, SDRAM but also supports and the like;
The starting address of a total of seven BANK0 ~ BANK6 BANK is fixed;
BANK7 programmable starting address selection;
BANK6, BANK7 address space is programmable control;
Each BANK of access cycles can be programmed;
The bus access cycle can be extended by an external "wait" signal;
When an external SDRAM, support for self-refresh (self-refresh) and a power-saving mode (power down mode)

12.2.2.2 S3C2440 associated with the storage pin

S3C2440 27 address lines drawn outside the access range ADDR0 ~ ADDR26 only 128MB (2 ^ 27)
External CPU 8 also leads to the chip select signal nGCS0 ~ nGCS7, corresponding to BANK0 ~ BANK7, when accessing the address space BANKx, nGCSx pin is cleared for the selected external device. Thus, each corresponding to 128MB nGCSx address space, to a total of 8 nGCSx signal corresponding to the address space 1GB.
There are on the data line 32, DATA0-DATA31. Control signal nOE, nWE, nWait, nGCS0-nGCS5 (Datasheet -P49)
Development board NORFlash DM9000 SDRAM connected on BANK (peripheral expansion bus mode)

12.2.3 hardware wiring diagram analysis

12.2.3.1 NOR Flash

JZ2440 is selected MX29LV160D T / B model, which is a 2M x 8bit or size 1M x 16bit, namely 2M / 1M space. 8/16 is a bit wide.

A0-A19: address line 2 ^ 20 = 1M
D0-D15: 16bit data line
BYTE: Select 16 / 8bit mode, directly connected to high level (16bit mode selected)
- Because the S3C2440 BANK0 only support (16bit / 32bit) of bits wide, and NOR Flash is connected to the BANK0, you can only choose 16 bit mode pulled
EC - NGCS0 (BANK0)
OE　WE　RESET
VCC　VSS
CPU_ADDR1 --- NOR_ADDR0 (ignoring the least significant bit)

12.2.3.2 SDRAM

BANK0 ~ BANK5 connections are similar, BANK6 complex connection point SDRAM, CPU provides a signal CS for the SDRAM --- BANK6, its first address 0x30000000
SDRAM clock valid signal SCKE; SDRAM clock signal SCLK0 / SCLK1
The data mask signal DQM0 / DQM1 / DQM2 / DQM3 (DQM control each 8bit, the front cover to prevent the write bit byte data -32bit operation)
SDRAM chip select signal nSCS0 (nGCS6 it functions the same two pins)
SDRAM row address strobe signal nSRAS
SDRAM column address strobe signal nSCAS
Write enable signal nWE (it is not dedicated to the SDRAM), is used in the JZ2440 EM63A165TS, the two 32M SDRAM

HY57V561620 (L) T Capacity: 4Banks x 4M x 16Bit = 32Mbyte, early

CPU needs 64Mbyte (26 address lines) 0x03 (0x00)
CPU_ADDR2---- SDRAM_ADDR0

SDRAM row address line 13, column address line nine (Row Address: RA0 ~ RA12, Column Address: CA0 ~ CA8), which are multiplexed
S3C2440 send an address to 0x30001000:
- When nSRAS valid, ADDR2-ADDR14 row address signal is sent, the corresponding bit [23-11]
- When nSCAS effective, ADDR2-ADDR10 column address signals are emitted, corresponding to the bit [10-2]
Referring to FIG hardware wiring on the manual data value, when the data line is 32, the lowest two bits is not used, a four byte address corresponds to the address and byte unity, then no bit [1-0 ] to the SDRAM.
note:
- logically:
  - Uses byte addressing mode, each address corresponds to a byte unit (regardless of the number of bytes of memory cells) arranged side -CPU
- Physically:
  - The storage unit: each address corresponding to the memory space is a memory unit
  - Total number of bytes of memory capacity = total number of bytes number X address memory means
  - To expand capacity by extending the address / data lines, such as our memory modules use 16M * 8bit memory chips, then we use the four particles words extended (data line), becomes 16M * 32bit, using four particles capacity expansion (address lines) becomes 64M * 8bit

12.3 memory controller

12.3.1 Timing Diagram

The timing of the control signal is the relationship between the expression of instruction execution in time, thanks to the timing IC to make methodical work.
Timing diagram of read method:
- From top to bottom, left to right, the high level, a low level in the next, in the middle of the high configuration.
- Double lines may also be high low, depending on data availability.
- Line indicates changes in the level crossing point state may be high to low, low to high may be, it can be unchanged.
Timing Diagram view:
- When the top-bottom and left to right, each to a point mutation (from 0 to 1, or from 1 to 0), the value of each signal is recorded, and further analysis shows their respective functions.

12.3.2 register settings

Total storage controller 13 registers, BANK0-BANK5 BWSCON only need to set and BANKCONx (x is 0-5) two registers;
BANK6、BANK7 外接 SDRAM 时，除 BWSCON 和 BANKCONx(x 为6、7)外，还需要设置 REFRESH、BANKSIZE、MRSRB6、MRSRB7 等 4 各寄存器：
- BWSCON：
  - STx 用于设置启用 UB/LB(0)
  - WSx 是否使用存储器的 WAIT 信号(0)
  - DWx 用于设置 BANK 位宽
- BANKCONx(x 为 0 - 5)：用于控制外接设备的访问时序，使用默认的 0x700 即可满足要求
- BANKCONx(x 为 6、7)：
  - MT[16 - 15] 设置接的是 ROM/SRAM[00] 还是 SDRAM[11]，如果是 00 的话，其他设备和 BANKCONx(x 为 0 - 5) 一样；当 MT 设置成 SDRAM 还需要设置 Trcd[3:2]，RAStoCAS(delay 设置推荐为 01)，Scan[1:0](SDRAM 列地址位数)

12.4 SDRAM 初始化

Makefile

 1 # 获取当前工作目录
 2 CURRDIR = $(shell pwd)
 3 
 4 # 头文件所在目录
 5 INCDIR = $(CURRDIR)
 6 
 7 # 交叉编译工具链的绝对路径
 8 CROSS_COMPILE = ~/work/s3c2440/tools/gcc-3.4.5-glibc-2.3.6/bin/arm-linux-
 9 
10 # 编译器工具
11 AS            = $(CROSS_COMPILE)as
12 LD            = $(CROSS_COMPILE)ld
13 CC            = $(CROSS_COMPILE)gcc
14 CPP            = $(CC) -E
15 AR            = $(CROSS_COMPILE)ar
16 NM            = $(CROSS_COMPILE)nm
17 STRIP        = $(CROSS_COMPILE)strip
18 OBJCOPY        = $(CROSS_COMPILE)objcopy
19 OBJDUMP        = $(CROSS_COMPILE)objdump
20 
21 # 编译器标识位设置
22 CFLAGS :=
23 AFLAGS :=
24 LDFLAGS :=
25 CFLAGS    :=
26 AFLAGSL    :=
27 
28 # 目标文件设置
29 objs := startup.o sdram.o
30 
31 all: clean s3c2440.bin
32 
33 
34 # 执行编译的过程
35 s3c2440.bin: $(objs)
36     $(LD) -Ttext 0x00000000 -o s3c2440_elf $^
37     $(OBJCOPY) -O binary -S s3c2440_elf $@
38     $(OBJDUMP) -D -m arm s3c2440_elf > s3c2440.dis
39 
40 
41 %.o:%.c
42     $(CC)  -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer -ffreestanding -c -o $@ $<
43 
44 %.o:%.S
45     $(CC)  -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer -ffreestanding -c -o $@ $<
46 
47 clean:
48     rm -f *.bin *_elf *.dis *.o

startup.S

  1 .equ        MEM_CTL_BASE,       0x48000000
  2 .equ        SDRAM_BASE,         0x30000000
  3 
  4 .text
  5 .global _start
  6 _start:
  7     bl  disable_watch_dog               @ 关闭WATCHDOG，否则CPU会不断重启
  8     bl  memsetup                        @ 设置存储控制器
  9     bl  copy_steppingstone_to_sdram     @ 复制代码到SDRAM中
 10     ldr pc, =on_sdram                   @ 跳到SDRAM中继续执行
 11 
 12 @ 栈是先入后出，SDRAM 的地址为 0x30000000，64M 大小的结束地址为 0x34000000
 13 on_sdram:
 14     ldr sp, =0x34000000                 @ 设置堆栈, 此时 pc 指向了栈顶
 15     bl  main
 16 
 17 halt_loop:
 18     b   halt_loop
 19 
 20 @ WTCON 寄存器允许用户使能或禁止看门狗定时器、从 4 个不同源选择时钟信号、使能或禁止中断和使能或禁止看门狗定时器输出。
 21 @ 看门狗定时器是用于恢复 S3C2440A 上电后若有故障重时新启动；如果不希望控制器重新启动，则应该禁止看门狗定时器。
 22 @ 如果用户希望使用看门狗定时器作为普通定时器，则应使能中断并且禁止看门狗定时器。
 23 @ STR{条件}  源寄存器，<存储器地址>
 24 @ STR指令用于从源寄存器中将一个 32 位的字数据传送到存储器中。
 25 disable_watch_dog:
 26     @ 往 WATCHDOG 寄存器写 0 即可，操作 WTCON 寄存器
 27     mov r1,     #0x53000000
 28     mov r2,     #0x0
 29     str r2,     [r1]
 30     mov pc,     lr      @ 返回
 31 
 32 @ S3C2440A 引导代码可以在外部 NAND Flash 存储器上执行。
 33 @ 为了支持 NAND Flash 的 BootLoader，S3C2440A 配备了一个内置的 SRAM 缓冲器，叫做“Steppingstone”。
 34 @ 引导启动时，NAND Flash 存储器的开始 4K 字节将被加载到 Steppingstone 中并且执行加载到 Steppingstone 的引导代码。
 35 copy_steppingstone_to_sdram:
 36     @ 将Steppingstone 的 4K 数据全部复制到 SDRAM 中去
 37     @ Steppingstone 起始地址为 0x00000000，SDRAM 中起始地址为 0x30000000
 38 
 39     mov r1, #0
 40     ldr r2, =SDRAM_BASE
 41     mov r3, #4*1024
 42 1:
 43     ldr r4, [r1],#4     @ 从Steppingstone读取4字节的数据，并让源地址加4
 44     str r4, [r2],#4     @ 将此4字节的数据复制到SDRAM中，并让目地地址加4
 45     cmp r1, r3          @ 判断是否完成：源地址等于Steppingstone的未地址？
 46     bne 1b              @ 若没有复制完，继续
 47     mov pc,     lr      @ 返回
 48 
 49 @ 存储控制器设置
 50 memsetup:
 51     @ 设置存储控制器以便使用SDRAM等外设
 52 
 53     mov r1,     #MEM_CTL_BASE       @ 存储控制器的13个寄存器的开始地址
 54     adrl    r2, mem_cfg_val         @ 这13个值的起始存储地址
 55     add r3,     r1, #52             @ 13*4 = 54
 56 1:
 57     ldr r4,     [r2], #4            @ 读取设置值，并让r2加4
 58     str r4,     [r1], #4            @ 将此值写入寄存器，并让r1加4
 59     cmp r1,     r3                  @ 判断是否设置完所有13个寄存器
 60     bne 1b                          @ 若没有写成，继续
 61     mov pc,     lr                  @ 返回
 62 
 63 .align 4
 64 mem_cfg_val:
 65     @ 存储控制器13个寄存器的设置值
 66     @ BWSCON 总线宽度和等待控制寄存器
 67     @ ‭0010 0010 0000 0001 0001 0001 0001 0000‬
 68     .long   0x22011110      @ BWSCON
 69     @ BANKCON0 Bank0 控制寄存器
 70     @ ‭0000 0000 0000 0000 0000 0111 0000 0000‬
 71     @ 设置了访问周期为 14 各时钟
 72     .long   0x00000700      @ BANKCON0
 73     @ BANKCON1 Bank· 控制寄存器
 74     .long   0x00000700      @ BANKCON1
 75     @ BANKCON2 Bank2 控制寄存器
 76     .long   0x00000700      @ BANKCON2
 77     @ BANKCON3 Bank3 控制寄存器
 78     .long   0x00000700      @ BANKCON3
 79     @ BANKCON4 Bank4 控制寄存器
 80     .long   0x00000700      @ BANKCON4
 81     @ BANKCON5 Bank5 控制寄存器
 82     .long   0x00000700      @ BANKCON5
 83     @ BANKCON6 Bank6 控制寄存器
 84     @ 0000 0000 0000 ‭0001 1000 0000 0000 0101‬
 85     @ 0 - 16 bit 有效：
 86     @ [16:15] 11：即 MT 设置为同步 DRAM 即 SDRAM
 87     @ 存储器类型 = ROM 或 SRAM [MT=00]（15 位），下面的数据设置为0，只有[3:0]有效
 88     @ [14:13] 
 89     @ [12:11]
 90     @ [10:8]
 91     @ [7:6]
 92     @ [5:4]
 93     @ 存储器类型 = SDRAM [MT=11]（4 位）时候：
 94     @ [3:2] 01：Trcd RAS 到 CAS 的延迟，设置为 3 各时钟(根据 SDRAM 的芯片手册设置)
 95     @ [1:0] 01：SCAN 列地址数，设置为 9 列，同样根据 SDRAM 手册设置
 96     .long   0x00018005      @ BANKCON6
 97     @ BANKCON7 Bank7 控制寄存器
 98     .long   0x00018005      @ BANKCON7
 99     @ REFRESH SDRAM 刷新控制寄存器 [24: 0] 有效
100     @ ‭0000 0000 1000 1100 0000 0111 1010 0011‬
101     @ 具体看芯片手册
102     .long   0x008C07A3      @ REFRESH
103     .long   0x000000B1      @ BANKSIZE 可变 Bank 大小寄存器
104     @ 当代码在 SDRAM 中运行时一定不要改变 MRSR 寄存器
105     @ 睡眠模式中，SDRAM 必须使能 SDRAM 自刷新模式
106     .long   0x00000030      @ MRSRB6 模式寄存器组寄存器 Bank6
107     .long   0x00000030      @ MRSRB7

sdram.c

 1 /**
 2  * 将0x56000050 强转为 unsigned long 型指针，并取这个地址的值
 3  * volatile 关键字：防止编译器优化，在应用层上多线程变量，在嵌入式中外设寄存器
 4  */
 5 #define GPFCON      (*(volatile unsigned long *)0x56000050)
 6 #define GPFDAT      (*(volatile unsigned long *)0x56000054)
 7 #define GPFUP       (*(volatile unsigned long *)0x56000058)
 8 
 9 /** 设置 GPFCON 的 4 5 6 引脚为输出 */
10 #define GPF4_OUT    (1 << (4 * 2))
11 #define GPF5_OUT    (1 << (5 * 2))
12 #define GPF6_OUT    (1 << (6 * 2))
13 
14 static void delay_ms(unsigned long ms);
15 
16 int main(void)
17 {
18     /** 将LED1-3对应的GPF4/5/6三个引脚设为输出 */
19     GPFCON = GPF4_OUT | GPF5_OUT | GPF6_OUT;
20 
21     unsigned long i = 0;
22     while(1){
23         delay_ms(500);
24         GPFDAT = (~(i<<4));         // 根据i的值，点亮LED1,2,4
25         if(++i == 8)
26             i = 0;
27     }
28 }
29 
30 static void delay_ms(unsigned long ms)
31 {
32     unsigned int i;
33 
34     while(ms--) {
35         for(i = 0; i < 1200; i++);
36     }
37 }