To use the memory controller setting register (special function register)
BWSCON 0x48000000 Bus width & wait status control register
STn Determines SRAM for using UB/LB for bank n
This I do not understand what it means, who knows what to tell ah.
WSn Determines WAIT status for bank n
WAIT state is enabled, then enable access to peripheral devices will wait?
DWn Determines data bus width for bank n
Decision bit width can be set to 8, 16 or 32
But no DW0, because bank0 bit width is determined by the external pin OM0 and OM1.
BANKCONn Bank control register
For bank0 to bank5 these timing settings are generally used can be a reset value without modification.
Tacs
Address set-up time before nGCSn
Tcos
Chip selection set-up time before nOE
Tacc
Access cycle
Tcoh
Chip selection hold time after nOE
Tcah
Address hold time after nGCSn
Tacp
Page mode access cycle @ Page mode
PMC
Page mode configuation
BANKCON6 / BANKCON7 and other bank is not the same, because both use the bank is the only bank of SDRAM
MT
the Determine at The Memory of the type set to 11 SDRAM
Trcd
RAS to CAS delay
SCAN
Column address number
REFRESH
SDRAM refresh control register
REFEN
SDRAM refresh enable
TREFMD
SDRAM refresh mode
Trp
SDRAM RAS pre-charge time
Tsrc
SDRAM semi row cycle time
Refresh Counter
This value is very important, is not set can not be used for external SDRAM
Refresh period = (2^11-refresh_count+1)/HCLK
For example, when the refresh cycle is 7.8us, HCLK is 100MHz
Refresh count=2^11+1-7.8*100=1269
BANKSIZE
flexible bank size register
There are many other settings
BURST_EN
ARM core burst operation enable
SCKE_EN
SDRAM power down mode enable control by SCKE
SCLK_EN
BK76MAP
This can be set to 001 64MB / 64MB
MRSRB6/MRSRB7
mode register set register bank n
----- above excerpt: http://blog.chinaunix.net/uid-26563605-id-3137271.html blog content