First look at the overall block diagram of the S3C2440 clock:
CPU works on FCLK FCLK UP TO 400MHZ
AHB works on HCLK HCLK UP TO 136MHZ
APB works on PCLK PCLK UP TO 68MHZ
How to get the above clock frequency (clock source: 12M crystal oscillator): The above three required clocks can be obtained through the PLL phase-locked loop
S3C2440 has two PLLs, one MPLL provides the clock to the CPU and the other UPLL provides the clock to the USB device.
There are two clock sources for S3C2440: 1: External clock source EXTCLK
2: External crystal oscillator
The external clock mode can be selected through the OM[3:2] pin, and the clock source can be selected through the OM3 OM2 pin level.
The FCLK obtained by the MPLL is provided to the CPU
HCLK is obtained by dividing the frequency by HDIVN
PCLK is obtained by dividing the frequency of PDIVN
It can be seen from the above block diagram that the clock frequency can be set by setting the register to control the MPLL HDIV PDIV.
Used to set Lock Time
/*Set MPLL FCLK:HCLK:PCLKI=400:100:50*/
/ * LOCKTIME (0X4C000000) = 0XFFFFFFFF * /
ldr r0, = 0x4c000000
ldr r1,=0xffffffff
str r1,[r0]
The divided frequency of HCLK and PCLK can be set by setting the CLKDIVN register
/*CLKDIVN(0X4C000014)=0X5,tFCLK:tHCLK:tPCLK=1:4:8*/
ldr r0, = 0x4c000014
ldr r1,=0x5
str r1,[r0]
When HDIVN is not 0, it is necessary to set the CPU to work in asynchronous mode, otherwise the operating frequency of the CPU is the frequency generated by HCLK
/* Set the CPU to work in asynchronous mode */
mrc p15,0,r0,c1,c0,0
orr r0,r0,#0xc0000000 //R1_nF:OR:R1_iA
mcr p15,0,r0,c1,c0,0
Set MPLL to let FCLK output 400M,
M=92
P=1
S=1
MPLL can be set by setting MDIV PDIV SDIV register
Set the FCLK frequency to 400M
/*Set MPLLCON(0X4C000004)=(92<<12)|(1|4)|(1<<0)
m=MDIV+8=92+8=100
P=PDIV+2=1+2=3
S=SDIV=1
FCLK=2*M*Fin/(P*2^S)=2*100*12/(3*2^1)=400m
*/
ldr r0, = 0x4c000004
ldr r1,=(92<<12)|(1<<4)|(1<<0)
str r1,[r0]
The following is the assembly code to configure the S3C2440 clock:
/*Set MPLL FCLK:HCLK:PCLKI=400:100:50*/
/ * LOCKTIME (0X4C000000) = 0XFFFFFFFF * /
ldr r0, = 0x4c000000
ldr r1,=0xffffffff
str r1,[r0]
/*CLKDIVN(0X4C000014)=0X5,tFCLK:tHCLK:tPCLK=1:4:8*/
ldr r0, = 0x4c000014
ldr r1,=0x5
str r1,[r0]
/* Set the CPU to work in asynchronous mode */
mrc p15,0,r0,c1,c0,0
orr r0,r0,#0xc0000000 //R1_nF:OR:R1_iA
mcr p15,0,r0,c1,c0,0
/*Set MPLLCON(0X4C000004)=(92<<12)|(1|4)|(1<<0)
m=MDIV+8=92+8=100
P=PDIV+2=1+2=3
S=SDIV=1
FCLK=2*M*Fin/(P*2^S)=2*100*12/(3*2^1)=400m
*/
ldr r0, = 0x4c000004
ldr r1,=(92<<12)|(1<<4)|(1<<0)
str r1,[r0]
/* Once the PLL is set, lock the lock time until the PLL output is stable
Then the CPU works at the new frequency FCLK
*/