FPGA Verilog编译时警告Warning (10230): truncated value with size 32 to match size of target (3)

Full warning:

Warning (10230): Verilog HDL assignment warning at digital_clock.v(75): truncated value with size 32 to match size of target 

the reason:

When writing Verilog counting programs, many people or many tutorials write like this:

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        cnt <= 0;
    end
    else if(add_cnt)begin
        if(end_cnt)
            cnt <= 0;
        else
            cnt <= cnt + 1;
    end
end

The 1 in cnt <= cnt + 1; does not specify the bit width, the system will automatically allocate a 32-bit bit width, which will waste resources, so the compiler will warn.

solve:

Write it as cnt <= cnt + 1'b1;

After the change:

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        cnt <= 0;
    end
    else if(add_cnt)begin
        if(end_cnt)
            cnt <= 0;
        else
            cnt <= cnt + 1'b1;
    end
end